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[SOLVED] (vsim-3734) error by Modelsim DE 10.5

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dpaul

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I am using Modelsim DE 10.5, no syntax errors, Modelsim does a clean compilation and just before simulation begins I get the following error:

# ** Fatal: (vsim-3734) Index value 0 is out of range 1 to 16.
# Time: 0 ps Iteration: 0 Instance: /top_tb/top_inst/my_inst/example_gen(0)/mysub_mod_inst File: C:/Work/...../my_inst.vhd Line: 339
# FATAL ERROR while loading design
# Error loading design

It is surprising for me to get this error as I have previously successfully complied designs containing similar multiple module instantiations based on generics.

my_inst.vhd excerpt:

Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
USE ieee.math_real.all;
library work;
use work.my_pkg.all;

entity my_inst is
    generic ( COUNT  : natural := 16 -- Max count is 16
    );
    port(
    .
    .
    .
   );
end entity my_inst ;

architecture my_inst_rtl of my_inst is

-- all other signals declared
signal ahblite_haddr          : c_32b_16x; -- type c_32b_16x  is array (0 to 15)  of std_logic_vector(31 downto 0);
signal ahblite_hrdata         : c_32b_16x; -- so are other types declared inside the my_pkg.vhd file
signal ahblite_hready_s2m     : c_01b_16x;
signal ahblite_hready_m2s     : c_01b_16x;                 
signal ahblite_hresp          : c_01b_16x;
signal ahblite_htrans         : c_02b_16x;
signal ahblite_hwdata         : c_32b_16x;
signal ahblite_hwrite         : c_01b_16x;
signal ahblite_hsel           : c_01b_16x;
signal ahblite_hresp_m        : c_02b_16x;

--
  begin

  .
  .
  .

  -- Inst 16x mysub_mod.vhd

  example_gen: for i in 0 to (COUNT-1) generate
        mysub_mod_inst: entity work.mysub_mod(arch_rtl)
        generic map(
            CHANNEL_NR => 0,
            CLK_FREQ   => 125_000_000 -- 125MHz clock frequency
        )
        port map(
            rst_n_i             => rst_n_i,
            clk_i               => clk_125M_i,
            srst_n_i            => srst_125M_n_i,
            -- AHB Lite i/f (slave)
            hready_i            => ahblite_hready_m2s(i),
            hsel_i              => ahblite_hsel(i)      ,
            haddr_i             => ahblite_haddr(i)     ,
            htrans_i            => ahblite_htrans(i)    ,
            hwdata_i            => ahblite_hwdata(i)    ,
            hwrite_i            => ahblite_hwrite(i)    ,
            hrdata_o            => ahblite_hrdata(i)    ,
            hreadyout_o         => ahblite_hready_s2m(i),
            hresp_o             => ahblite_hresp(i)     ,
            -- Data i/f
            log_data_o    => log_data(i),
           log_we_o       => log_we(i)  ,
           log_end_o      =>log_end(i)
        );  --- Modelsim reports error here!!!
    end generate example_gen;
  .
  .

end architecture my_inst_rtl;
In the .do file, the vcom -2008 -explicit switch is used.

Even if I replace the generic declaration as COUNT : integer := 16 there is no effect.
What am I missing here?
 
Last edited:

TrickyDicky

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It would suggest one of the ports is declared as 1 to 16 rather than 0 to 15. Can you post the mysub_mod entity?
 

    dpaul

    points: 2
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dpaul

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Correct Tricky and thanks!
For the signals connecting mysub_mod, some of the 2D arrays were 0 to 15 while others were 1 to 16 (I had to dig inside the my_pkg.vhd package module). Didn't realize this easily on a Friday afternoon! :-D

But I had the expectation that Modelsim would point out to the line number where this mismatch was occurring (the particular port-map line). Instead it was complaining for Line: 339, where the module instantiation was ending.
 

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