voltage spike at output of AND gate

[cgchas]

I am getting voltage spikes on two of the outputs of an M74HC08 Quad 2-Input AND Gate. Only two of the 4 input sets are in use. The unused inputs are grounded.

Each of the inputs of the AND gate are being fed a square wave as well as one of the outputs of an SN74HC109 Dual Input JK Flip-flop in toggle mode. The unused inputs are grounded.

The first input of the AND gate is getting:
-square wave clock input
-J/K flip-flop Q output (toggle mode. uses the very same square wave input)

The second input of the AND gate is getting:
-square wave clock input
-J/K flip-flop Q complement output (toggle mode. uses the very same square wave input)

The resulting final 2 outputs are each phase correct to the input clock as well as half of the positive duty cycle which is what I require.



The problem is the voltage spikes.



Note that the spikes do not show in the first image, but are intermittently present on the output.
The second image shows the spikes more clearly at the higher clock frequency.

The clock itself has no spikes at any time.
The ouput of the flip-flop is clean as well. No spikes are there.
The spikes are only present on the outputs of the AND gate.

I am using 100nF decoupling capacitors with the IC's and have chosen chips from the same 74HC family.

I can remove the spikes if I place a small capacitor on the output signal, but that also affects the rise and fall time of the signal which I would like to avoid if possible.
What other steps can be taken?

Any comments are suggestions would be greatly appreciated.

 

[godfreyl]

IMHO, the problem is that the flip-flop introduces a slight delay so at the inputs to the AND gate, the clock signal goes high slightly before the flip-flop signal goes low.

If you can figure out the delay through the flip-flop, you can compensate by introducing a similar delay between the clock and the AND gate input it's connected to.

Maybe you could delay the signal by passing it through a couple of inverters, or just use an RC filter.

 

[cgchas]

IMHO, the problem is that the flip-flop introduces a slight delay so at the inputs to the AND gate, the clock signal goes high slightly before the flip-flop signal goes low.

If you can figure out the delay through the flip-flop, you can compensate by introducing a similar delay between the clock and the AND gate input it's connected to.

Maybe you could delay the signal by passing it through a couple of inverters, or just use an RC filter.

Thank you for your response.

You are correct regarding the flip-flop introducing a delay. I can tell because the oscilloscope doesn't trigger accurately off the main clock when displaying the 2 outputs of the AND gate. In order to use an external trigger, I have to take the signal off of one of the outputs of the flip-flop.

The flip-flop delay might also explain why the spikes are more consistent at higher clock frequencies.

I estimate the delay to be approximately 70nS based off the scope display. (top trace is flip-flop, bottom is clock)


Thank you.