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Voltage reference long-term stability

frankrose

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Hi all,

I have just read that reference circuit's long-term stability (>1000 hours accuracy) depend on packaging material a lot.

I am wondering what else can influence it if there any other factors which can be influenced by designer?

Like:
- technology used (manufacturer, process differences, number of used masks, buried/epitaxial/metal layer's effect, the type of devices, lateral/vertical transistors, leakage, etc.)
- circuit implemented (difference between circuit architectures, curvature compensation methods, bandgaps with/without OPAmps are better, auto-zero/choppering used or not, impedance level regarding noise, low flicker noise is essential, etc.)

Or simply packaging is the key element in long-term stability?

If you have any experience with design for long-term stability, please won't hesitate to share. Thank you in advance!
 

danadakk

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Some info here -



Regards, Dana.
 

dick_freebird

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There are multiple "drift" mechanisms in semiconductors and which a given technology is sensitive to, and how they manifest vary with construction from starting material to clipped package.

Oxide charging in bipolar op amps can come from front end EOS induced hot carriers. It can also be a "feature" of dry etch and plasma assisted or sputter deposition. Low quality oxides like LOCOS or STI have more bulk and surface traps to hold (for a while) charges where they can modify the "real" device.

The norm as I've observed it, is for the process guys to throw a lot of hydrogen at it. This can (at t=0) passivate traps. But you can get drift from detrapping charge just like trapping it. H+ is a mobile ion and any ionization of entrained hydrogen will allow a passivating H to become mobile, drift with applied fields (and create differential drifts if fields are asymmetric, as may be the designed or applied case). For example an op amp operated at closed loop input null is a more benign case than the exact same front end used as a comparator seeing gross differences in OP.

Use of nitride passivation is nearly universal these last few decades. The usual method of growing in ammonia ambient, entrains a -lot- of hydrogen, and the Si3N4 film is a great hydrogen barrier while the underlying oxides will allow the hydrogen load to diffuse throughout the chip, including to places it can be moved to or from that are electrically sensitive.

Si3N4 is popular because it is also a very effective mobile ion intrusion barrier. Lots of CMOS stability problems in the days of silox passivation and plastic packaging. Pick your poison.

There are other mechanisms too like basic HCE. Increase oxide charge over a BJT E-B junction, raise the surface recombination rate and you get Vbe drift and a big hurt on low current beta. Charge the edge-of-finger oxide on a NMOSFET (LOCOS bird's beak or STI sidewall) and see delta VT, leakage floor rise, potentially "gate kink" (good way to develop current mirror mismatch if the drift comes from discrepant Vds, which makes discrepant HCE conditions.
 

dick_freebird

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Packaging is IME always a struggle on precision single-ended circuits. The materials are one thing but packaging also imparts further thermal input and leaves mechanical strain on the die.

I am looking at this now since my latest Vref is showing < 0.1% trimmed initial accuracy on die @ probe but picking up a 3% drift across mount / bond / seal (w/ 2% spec).

Back in the day for Hi Rel Vrefs we would impose a "stab(ilization) bake" on wafers before probe/trim to drive any "undercooked" metallurgy (thin film resistors, contacts) to maximally stable. Otherwise packaging might do that, after trim (bad).

Using diffused / implanted resistors puts piezoresistive strain effects in play. Very sensitive to packaging flow, leadframe or cavity material and temp profile and die thinning (thinner die can resist stress, less so more strain). This is why you sometimes see two must-match resistors (like op amp "null" pins and maybe op amp based bandgap tail loads) laid out at 45 degrees, where crystallographic strain induced sheet resistance drift is minimized.
 

KlausST

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Hi,

I´ve once read an Linear Technology application note AN-82 about reference voltage stability.
They told that mechanical force will degarde stability. In the AN they told that high precision VRefs should be mounted with milling around three sides .. so that mechanical stress of the PCB does not affect the Ref IC.

I never experimented with this.

Klaus
 

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