Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Voltage levels on JTAG pins

Status
Not open for further replies.

shrutib

Newbie level 4
Joined
Aug 27, 2015
Messages
7
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
61
Hello,

I am using 10pin JTAG header and have follwing voltage levels on pins when device is powered on:
TMS = 3.3V
TCK = 3.3V
TDO = ~2mV
TDI = ~2mV
nRESET = 3.3V

The problem is the controller is not responding when connected to debugger. should the voltage levels at TDO and TDI be also 3.3V? Is this creating problem or there might be some other reason?
Thankyou in advance.
 

As far as my experience, all the JTAG pins are held at logic 1 unless another JTAG device isn't connected to the port.
 

Pull-ups are specified by the JTAG standard for TDI, TMS and TRST "undriven input produces a logical response identical to the application of a logic 1".
TDO should be high Z as long as the TAP controller is inactive.

In so far, measuring low level at TDI indicates a problem, possibly a PCB short or damaged device.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top