voltage interface 3.3V -> 1.8V on chip

[hans_r]

Hi,

I'm using the UMC180nm technology to design an image sensor: the thick oxide 3.3V transistors are used for increased swing when sensing the light. I want the digital parts of my circuit to work on 1.8V (reduces area!). I'm using a thick oxide inverter attached to 1.8V in stead of 3.3V. In Spectre this works, but it gives the warning that the bulk-drain junction leaves the linearized region. I know this is because of the high Vgs voltage at the pMOS when the input is 3.3V. Is this detrimental to my circuit, or will it work? Or is there maybe an other way to interface to the 1.8V transistors with the 3.3V?
Thanks!

 

[erikl]

I don't see any reasonable reason for the bulk-drain junction to leave the linearized region: when the input is 3.3V , the bulk-drain junction is just 1.8V (in reverse) -- no motive for any non-linearity. I guess this is a general warning generated for non-standard voltage levels, not dedicated nor reasonable for your application. And a negative blocking voltage of Vgs=3.3-1.8=1.5V for the 3.3V pMOS can't be a jeopardy, either.

So -- IMHO -- no problem!

 

[hans_r]

Thanks for the reply. I was worried this would be a point of discussion in the defense of my design.
I am glad you think this way. Kind regards...

 

[checkmate]

The phenomenon is called positive bias temperature instability (PBTI). The vth of the pmos will increase over time, resulting in degradation of propagation delay. If you can tolerate that, then it's no issue.

 

[erikl]

NBTI & PBTI are long time stress phenomena. I'd think the voltage differences occurring in this application aren't too significant for 3.3V (thick oxide) MOSFETs - all the more as this thick oxide isn't a high-k (SiO₂/HfO₂) material stack.