Voltage Controlled Delay Line (VCDL) for DLL

[spec07]

How does the VCDL control the delay output of the DLL? The input of the VCDL comes from the output of the charge pump. Am I correct that when the output of the charge pump increases, it will cause the delay lines of the VCDL to stop thus making the DLL output to be faster?

 

[camr]

My understanding of a VCDL is that the voltage from the charge pump determines the power supply voltage across the gates in the delay line, so when it varies, the gates become incrementally slower or faster in response. The input to the VCDL is your DLL clock signal, whose delay you are trying to control.