blowfish
Member level 4
Hi,
I require some design concepts and techniques involved in vlsi (vhdl/verilog with FPGA ) implementation of digital delay locked loop.Generally digital DLL consists of following components.
I.Phase detector
II.Digitally controlled delay unit
III. Digital controller
I am trying to use a Up/Down counter for the digital controller to produce digital control words, digital phase detector circuit using some flip flops with gates and flip flops (d flip flops) as individual delay unit blocks. Will this work corrcetly. Necessary suggestions and solutions will be appreciated .
I require some design concepts and techniques involved in vlsi (vhdl/verilog with FPGA ) implementation of digital delay locked loop.Generally digital DLL consists of following components.
I.Phase detector
II.Digitally controlled delay unit
III. Digital controller
I am trying to use a Up/Down counter for the digital controller to produce digital control words, digital phase detector circuit using some flip flops with gates and flip flops (d flip flops) as individual delay unit blocks. Will this work corrcetly. Necessary suggestions and solutions will be appreciated .