Hi
The frontend is writing RTL , linting and Verifying the RTL using testbenches and testcases.
Synthesis aids as an interface for frontend and backend.
Backend encompases ur static timing analysis,floorplanning,clock tree synthesis, layout,signal integrity issues,frormal verification etc.
As far as VHDL is concerned its scope lies under frontend only.Some simulators may be used for post layout simulation.
The vendors providing tools are :
Synopsys
Cadence
Magma
Tanner
Mentor Graphics
fintronics
bye,