vlsi design verification

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I'm hearing the term for first time. Few minutes of googling tells me this: A new approach to verification which is a mix of formal verification and simulation. It is a coverage driven simulation where the un-covered parts of code in simulation is detected and input stimulus are generated accoringly.

This ppt from Stanford Uni can give you a better idea
verify.stanford.edu/TALKS/iccad99.ppt
 
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