[SOLVED] VLSI design project ideas for final year

[yaju1984]

Hi
I am studying Mtech VLSI design, and am in my final year.
I am searching for project topics for my final project.
Can anybody suggest any IEEE projects, or any other project ideas?
I am interested in Digital design, VHDL, Verilog.
Any help will be apreciated.

 

[srinivasansreedharan]

Hi,
You can try with AES which is datapath oriented design or I2C which is a controller oriented design. These are quite simple to work with. Alternatively you can also design an efficient ALU.

 

[somu.atluri]

SRAM design and layout??

Involves both VHDL/Verilog and also designing some cells at transistor level.

you can do layout if u r interested.

 

[gliss]

Why would SRAM design necessarily involve both VHDL and Verilog?

 

[somu.atluri]

oops.. by both -i mean VHDL/verilog and cell design

 

[ljxpjpjljx]

try to do bus protocol design!

 

[yaju1984]

Thanks Guys
I'm Looking into the Ideas You suggested
Any Ideas in Analog Design?
The project should preferrably last for one whole year.

 

[somu.atluri]

how about ADC/DAC design.
if u want a bit more complicated.. PLL.

Good luck.

 

[jaydip]

i would suggest to design Intel's 8255, 8237 etc designs .. those are the very basic but includes all complexities one wishes to have ... also, those are protocols you must have studied already, u need not read protocol docs as well ..

all the best ..

 

[majestic.eda]

hi yaju

i think I2C, SRAM design r indeed good ideas..
ask anoop.. he has some material on "SRAM Cells with sleepy transistors"

--- Vicky here! all d best

 

[somu.atluri]

hi vicky,

i just started working on SRAM cell.. never came across sleepy transistors... can u briefly tell me wats that? and who is anoop, how do i contact him,?

thanks in adv.

 

[majestic.eda]

Well, as u might be knowing that in today's VLSI design, the sub-threshold current becomes the one of the major factors of the power consumption, especially when u design a memory chip.


Here's some extract I found in one such project report online...

To reduce the leakage power in the SRAM, the power gating method can be applied and a major technique of the power gating is using sleep transistors to control the sub-threshold current.

In this project, dual threshold voltages are adopted; normal SRAM cells have lower threshold voltages and THE higher threshold voltages control the sleep transistors. The size of sleep transistors can be chosen by the worst case current and are applied to every block.


I had a paper on this subject but i think i'd lost it..

Added after 3 minutes:

@ Somu

Hey.. Check this out: https://www.scribd.com/doc/23194047/32K-BIT-SLEEPY-SRAM

 

[somu.atluri]

thanks man, the link has good information.