vlsi chip designing.....

[Muthuraja.M]

Hi friends i want to know about power gating .

How it reduces the power consumption ?

Pls explain with an example.

Design a counter using power gated circuit...


Thanks in advance

 

[Venkadesh_M]

consider a module having three inputs i clk load and one output o

---

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity normalclk is
port( clk : in std_logic;
      load : in std_logic;
      i : in std_logic;
     o : out std_logic
      );    
end normalclk;
 
 
architecture Behavioral of normalclk is
 
BEGIN
process(clk)
begin
if(rising_edge(clk)) then
if(load ='1') then
o <= i;
end if;
end if;
end process;
 
end Behavioral;

---

same with power Gated clock

---

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity gatedclk is
port( clk : in std_logic;
      load : in std_logic;
      i : in std_logic;
      o : out std_logic
      );    
end gatedclk;
 
architecture Behavioral of gatedclk is
signal gclk : std_logic;
 
BEGIN
gclk <= clk and load;
process(gclk)
begin
if(rising_edge(gclk)) then
o <= i;
end if;
end process;
 
end Behavioral;

---

doing the operation when the result is needed that is power gating....

 

[Muthuraja.M]

Thanks for ur reply..

Can u please explain in verilog code.. And u r using gatedclk=clk and load wat is the use of it over a normal clock. pls explain the diference

 

[Venkadesh_M]

in normal clock the clock is the clk
but in gated mode you are masking the gate with the input load

---

Code VHDL - [expand]
1
gclk <= clk and load

---

 

[Muthuraja.M]

ok fine . But wat is the different in their output responses.

Is this method reduces the power . If means How ?

Please explain....

 

[Venkadesh_M]

you want do a process If it is not necessary.. Are you got if??

 

[Muthuraja.M]

simulate your code . But i dont find the difference between the two. Thatswhy i am asking you.

Pls explain wats the difference happens btween the two..

- - - Updated - - -

I simulate your code . But i dont find the difference between the two. Thatswhy i am asking you.

Pls explain wats the difference happens btween the two..

 

[Venkadesh_M]

ok then lets consider an application if today is Wednesday you have to pay money for chocolates you are getting 10 of each 50paise

then you don need to multiply if its not Wednesday...

 

[Muthuraja.M]

Rite. But in case of these two codes both the outputs are dependent of both the load and the clk.

So which makes the difference in their responses.

And so how it is different when their dependent parameters are same.

 

[Venkadesh_M]

the process of loading o<=i will be only carried out if the load is high..

 

[Muthuraja.M]

Now only I understand ur explanation.

Thanks for your nice explanation...

It relates with the physical implementations rite. If these two are implemented means the gated clk has the kow power compared to the normal clk.

Pls reply me . Am i correct ?

- - - Updated - - -

Now only I understand ur explanation.

Thanks for your nice explanation...

It relates with the physical implementations rite. If these two are implemented means the gated clk has the low power compared to the normal clk.

Pls reply me . Am i correct ?

 

[Venkadesh_M]

correct....

 

[Muthuraja.M]

Thank u very much....

 

[rca]

Well your question was about power gating and not clock gating right?
So the nice chats exchanged were about clock gating.

For the power gating, the logic are separate on multiple row-island, which the power supply of each island could be control over the time.
The power gating could also be apply on memories.

 

[Muthuraja.M]

Yeah right. Anyway no problem i also want to know about clock gating.. So its useful only.. Thanks for telling that your answers belongs to clock gating.....

Among these two methods which is effective to reduce power consumption ?

 

[rca]

The clock gating is efficient and "easy" to add during RTL coding or add during the synthesis step.
The power gating required time for backend flow by adding CPF or UPF on synthesis/PnR/ATPG/LEC/STA...

 

[Muthuraja.M]

Okay .... I am clear about clock gating . But may be some of the doubts arise in power gating.

Clarify me whenever needed.....

 

[Venkadesh_M]

sorry slightly confused with gating for power consumption...

 

[Muthuraja.M]

Okay .......

 

[childs72]

Well your question was about power gating and not clock gating right?
So the nice chats exchanged were about clock gating.

For the power gating, the logic are separate on multiple row-island, which the power supply of each island could be control over the time.
The power gating could also be apply on memories.

Is it possible to implement power gating through RTL code?