echoangel9111
Newbie level 5
Hello people, i was wondering who can help me solve this
a single transistor DRAM cell with a total storage of cap 10fF is refreshed at frequency of 1MHz using 5v supply. The read circuitry will detect voltages more or less than vdd/2. Due to processing variations, the cell leakage current when it is storing a logic 1 (ie 5V) is known to be uniformly distributed between 10nA and 40nA. Give a rough esimate of cell yield.
a single transistor DRAM cell with a total storage of cap 10fF is refreshed at frequency of 1MHz using 5v supply. The read circuitry will detect voltages more or less than vdd/2. Due to processing variations, the cell leakage current when it is storing a logic 1 (ie 5V) is known to be uniformly distributed between 10nA and 40nA. Give a rough esimate of cell yield.