At the risk of stating the obvious : It’s a timing constraint. In Vivado. It tells the tools how fast the FPGA has to run. As far as I know there’s nothing explicitly called a “Vivado timing constraint”.
It is Xilinx Design Constraint (.xdc) not "Vivado Timing Constraint ", which constrains the FPGA design as stated above.
Read the latest version of UG903 for details on XDCs.