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[SOLVED] Vivado Synthesis failed with No errors or warnning

MSAKARIM

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I'm working on a project with Vivado2017.4. I have "Synthesis Failed" result, but no error messages.
and i have a file( vivado.error.rst) file generated in <>.runs\synth_1\
How can i resolve this issue.
 

dpaul

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I guess you have seen this failure message in the Vivado TCL console.
Have you looked inside the synthesis log file?
If not, you need to go through the log file carefully to find out if the reason for failure is listed there or not.
 

MSAKARIM

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I guess you have seen this failure message in the Vivado TCL console.
Have you looked inside the synthesis log file?
If not, you need to go through the log file carefully to find out if the reason for failure is listed there or not.
I found this " An unexpected error has occurred (EXCEPTION_ACCESS_VIOLATION) "

Note: Vivado synthesized all other files properly only this file failed ( although it works well in simulation mode and i have the desired result)

Code:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_arith.all;
USE IEEE.STD_LOGIC_unsigned.all;


ENTITY SBOX IS 
PORT (CLK,RST: IN STD_LOGIC;
       SI: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
       SO: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END SBOX;

ARCHITECTURE SBOX OF SBOX IS
--COMPONENTS--
COMPONENT M1 is
port (a,b,c,d:in std_logic;
     Y: out std_logic_vector(7 downto 0));
end COMPONENT;
COMPONENT M2 is
port (a,b,c,d:in std_logic;
     Y: out std_logic_vector(7 downto 0));
end COMPONENT;
COMPONENT M3 is
port (a,b,c,d:in std_logic;
     Y: out std_logic_vector(7 downto 0));
end COMPONENT;
COMPONENT M4 is
port (a,b,c,d:in std_logic;
     Y: out std_logic_vector(7 downto 0));
end COMPONENT;
COMPONENT M5 is
port (a,b,c,d:in std_logic;
     Y: out std_logic_vector(7 downto 0));
end COMPONENT;
COMPONENT M6 is
port (a,b,c,d:in std_logic;
     Y: out std_logic_vector(7 downto 0));
end COMPONENT;
COMPONENT M7 is
port (a,b,c,d:in std_logic;
     Y: out std_logic_vector(7 downto 0));
end COMPONENT;
COMPONENT M8 is
port (a,b,c,d:in std_logic;
     Y: out std_logic_vector(7 downto 0));
end COMPONENT;
COMPONENT M9 is
port (a,b,c,d:in std_logic;
     Y: out std_logic_vector(7 downto 0));
end COMPONENT;
COMPONENT M10 is
port (a,b,c,d:in std_logic;
     Y: out std_logic_vector(7 downto 0));
end COMPONENT;
COMPONENT M11 is
port (a,b,c,d:in std_logic;
     Y: out std_logic_vector(7 downto 0));
end COMPONENT;
COMPONENT M12 is
port (a,b,c,d:in std_logic;
     Y: out std_logic_vector(7 downto 0));
end COMPONENT;
COMPONENT M13 is
port (a,b,c,d:in std_logic;
     Y: out std_logic_vector(7 downto 0));
end COMPONENT;
COMPONENT M14 is
port (a,b,c,d:in std_logic;
     Y: out std_logic_vector(7 downto 0));
end COMPONENT;
COMPONENT M15 is
port (a,b,c,d:in std_logic;
     Y: out std_logic_vector(7 downto 0));
end COMPONENT;
COMPONENT M16 is
port (a,b,c,d:in std_logic;
     Y: out std_logic_vector(7 downto 0));
end COMPONENT;
COMPONENT MUX1 IS
PORT(A0,A1,A2,A3: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
     D,C: IN STD_LOGIC;
     OUT1: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END COMPONENT;
COMPONENT REG4 IS
PORT ( CLK,RST: IN STD_LOGIC;
          A: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
          B: OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END COMPONENT;
COMPONENT REG8 IS
PORT ( CLK,RST: IN STD_LOGIC;
          A: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
          B: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END COMPONENT;

--SIGNALS--
SIGNAL AREG4,BREG4: STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL M1OUT, M2OUT,M3OUT,M4OUT,M5OUT,M6OUT,M7OUT,M8OUT,M9OUT,M10OUT,M11OUT,M12OUT,M13OUT,M14OUT,M15OUT,M16OUT,MXOUT1,MXOUT2,MXOUT3,MXOUT4,MXOUT5,REG80,REG81,REG82,REG83 : STD_LOGIC_VECTOR (7 DOWNTO 0);
sIGNAL  MM1OUT, MM2OUT,MM3OUT,MM4OUT,MM5OUT,MM6OUT,MM7OUT,MM8OUT,MM9OUT,MM10OUT,MM11OUT,MM12OUT,MM13OUT,MM14OUT,MM15OUT,MM16OUT : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN

AREG4 <= SI(3)&SI(2)&SI(1)&SI(0);



REG1: REG4 PORT MAP (CLK,RST,AREG4,BREG4);

MA1: M1 PORT MAP (BREG4(3),BREG4(2),BREG4(1),BREG4(0),M1OUT);
MA2: M2 PORT MAP (BREG4(3),BREG4(2),BREG4(1),BREG4(0),M2OUT);
MA3: M3 PORT MAP (BREG4(3),BREG4(2),BREG4(1),BREG4(0),M3OUT);
MA4: M4 PORT MAP (BREG4(3),BREG4(2),BREG4(1),BREG4(0),M4OUT);
MA5: M5 PORT MAP (BREG4(3),BREG4(2),BREG4(1),BREG4(0),M5OUT);
MA6: M6 PORT MAP (BREG4(3),BREG4(2),BREG4(1),BREG4(0),M6OUT);
MA7: M7 PORT MAP (BREG4(3),BREG4(2),BREG4(1),BREG4(0),M7OUT);
MA8: M8 PORT MAP (BREG4(3),BREG4(2),BREG4(1),BREG4(0),M8OUT);
MA9: M9 PORT MAP (BREG4(3),BREG4(2),BREG4(1),BREG4(0),M9OUT);
MA10: M10 PORT MAP (BREG4(3),BREG4(2),BREG4(1),BREG4(0),M10OUT);
MA11: M11 PORT MAP (BREG4(3),BREG4(2),BREG4(1),BREG4(0),M11OUT);
MA12: M12 PORT MAP (BREG4(3),BREG4(2),BREG4(1),BREG4(0),M12OUT);
MA13: M13 PORT MAP (BREG4(3),BREG4(2),BREG4(1),BREG4(0),M13OUT);
MA14: M14 PORT MAP (BREG4(3),BREG4(2),BREG4(1),BREG4(0),M14OUT);
MA15: M15 PORT MAP (BREG4(3),BREG4(2),BREG4(1),BREG4(0),M15OUT);
MA16: M16 PORT MAP (BREG4(3),BREG4(2),BREG4(1),BREG4(0),M16OUT);

BeforeMUX1: REG8 PORT MAP (CLK,RST,M1OUT, MM1OUT);
BeforeMUX2: REG8 PORT MAP (CLK,RST,M2OUT,  MM2OUT);
BeforeMUX3: REG8 PORT MAP (CLK,RST,M3OUT,  MM3OUT);
BeforeMUX4: REG8 PORT MAP (CLK,RST,M4OUT,  MM4OUT);
BeforeMUX5: REG8 PORT MAP (CLK,RST,M5OUT,  MM5OUT);
BeforeMUX6: REG8 PORT MAP (CLK,RST,M6OUT,  MM6OUT);
BeforeMUX7: REG8 PORT MAP (CLK,RST,M7OUT,  MM7OUT);
BeforeMUX8: REG8 PORT MAP (CLK,RST,M8OUT,  MM8OUT);
BeforeMUX9: REG8 PORT MAP (CLK,RST,M9OUT,  MM9OUT);
BeforeMUX10: REG8 PORT MAP (CLK,RST,M10OUT,  MM10OUT);
BeforeMUX11: REG8 PORT MAP (CLK,RST,M11OUT,  MM11OUT);
BeforeMUX12: REG8 PORT MAP (CLK,RST,M12OUT,  MM12OUT);
BeforeMUX13: REG8 PORT MAP (CLK,RST,M13OUT,  MM13OUT);
BeforeMUX14: REG8 PORT MAP (CLK,RST,M14OUT,  MM14OUT);
BeforeMUX15: REG8 PORT MAP (CLK,RST,M15OUT,  MM15OUT);
BeforeMUX16: REG8 PORT MAP (CLK,RST,M16OUT,  MM16OUT);



MX1: MUX1 PORT MAP (MM1OUT,MM2OUT,MM3OUT,MM4OUT, SI(5),SI(4),MXOUT1);
MX2: MUX1 PORT MAP (MM5OUT,MM6OUT,MM7OUT,MM8OUT, SI(5),SI(4),MXOUT2);
MX3: MUX1 PORT MAP (MM9OUT,MM10OUT,MM11OUT,MM12OUT, SI(5),SI(4),MXOUT3);
MX4: MUX1 PORT MAP (MM13OUT,MM14OUT,MM15OUT,MM16OUT, SI(5),SI(4),MXOUT4);

AREG8: REG8 PORT MAP (CLK,RST,MXOUT1, REG80);
BREG8: REG8 PORT MAP (CLK,RST,MXOUT2, REG81);
CREG8: REG8 PORT MAP (CLK,RST,MXOUT3, REG82);
DREG8: REG8 PORT MAP (CLK,RST,MXOUT4, REG83);

MX5: MUX1 PORT MAP (REG80,REG81,REG82,REG83,SI(7),SI(6),MXOUT5);

EREG8: REG8 PORT MAP (CLK,RST,MXOUT5,SO);



END SBOX;
All sub-modules are synthesized well and i have no syntax error,
when i google this issue i found this:" https://www.xilinx.com/support/answers/66106.html " , but i dont know how to apply it
 

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As the file is just a bunch of instantiated components. I suggest instead of using positional port mapping to explicitly map the ports. I've seen Vivado and ISE before have issues with valid code that just doesn't synthesize correctly or throws errors unless you change/avoid some specify coding style.

Maybe the QA testing runs the tools on files with port mapping using the "=>", so it's hit or miss with positional mapping.

Why does this file have the libraries USE IEEE.STD_LOGIC_arith.all; and USE IEEE.STD_LOGIC_unsigned.all; called out, neither are used in this file? You should clean stuff like that up. If this is legacy IP code...I would have rejected it's submission, due to unused libraries, using positional port mapping, poor/inconsistent formatting of the code, lack of a header and description, date, change log (but maybe that is part of the source control), etc.

IMO the standard for code that could be or will be reused should be held to a much higher level of quality than code that will never be reused.
 

vGoodtimes

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that looks like codegen code. i'm guessing any comments would be there. I don't think std_logic_unsigned is related anymore than the excessive use of caps.

access violation likely means something in the synthesis flow crashed -- for a memory access violation. the linked AR shows how unexpected return codes affect the tool and this exception code would become the return code. either way, I'd update/change the tool if possible as this sounds like a programming error. It might be a regression and fixed by downgrading, or it might be a bug fixed in a newer version.
 

MSAKARIM

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As the file is just a bunch of instantiated components. I suggest instead of using positional port mapping to explicitly map the ports. I've seen Vivado and ISE before have issues with valid code that just doesn't synthesize correctly or throws errors unless you change/avoid some specify coding style.

Maybe the QA testing runs the tools on files with port mapping using the "=>", so it's hit or miss with positional mapping.

Why does this file have the libraries USE IEEE.STD_LOGIC_arith.all; and USE IEEE.STD_LOGIC_unsigned.all; called out, neither are used in this file? You should clean stuff like that up. If this is legacy IP code...I would have rejected it's submission, due to unused libraries, using positional port mapping, poor/inconsistent formatting of the code, lack of a header and description, date, change log (but maybe that is part of the source control), etc.

IMO the standard for code that could be or will be reused should be held to a much higher level of quality than code that will never be reused.
I tried this solution but i still have the same problem.

- - - Updated - - -

that looks like codegen code. i'm guessing any comments would be there. I don't think std_logic_unsigned is related anymore than the excessive use of caps.

access violation likely means something in the synthesis flow crashed -- for a memory access violation. the linked AR shows how unexpected return codes affect the tool and this exception code would become the return code. either way, I'd update/change the tool if possible as this sounds like a programming error. It might be a regression and fixed by downgrading, or it might be a bug fixed in a newer version.
i'm wondering about "why this file!!, all other files in the same project or other projects are synthesized properly "
 

std_match

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Maybe your computer runs out of RAM when processing this file.
How much RAM do you have?
 

MSAKARIM

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vGoodtimes

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the problem probably isn't the file but some combination of files. I'm guessing that synthesizing just the posted file will not crash. just complain about missing blackboxes.
 

MSAKARIM

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the problem probably isn't the file but some combination of files. I'm guessing that synthesizing just the posted file will not crash. just complain about missing blackboxes.
All sub-modules of this main module are synthesized well ( i checked them one by one).
 

TrickyDicky

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Unfortunately I have found crashes like these are sometimes the interplay between modules.
Usually the only way to find this is to remove modules one at a time until the crash stops. Then when you've found the offending module, then go through removing process by process until you find the offending code.
You are also using an outdated version of Vivado (>2 years old). Any chance you could update to 2019.2?
 

MSAKARIM

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Unfortunately I have found crashes like these are sometimes the interplay between modules.
Usually the only way to find this is to remove modules one at a time until the crash stops. Then when you've found the offending module, then go through removing process by process until you find the offending code.
You are also using an outdated version of Vivado (>2 years old). Any chance you could update to 2019.2?
I will try to use it as soon as possible
 

MSAKARIM

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Unfortunately I have found crashes like these are sometimes the interplay between modules.
Usually the only way to find this is to remove modules one at a time until the crash stops. Then when you've found the offending module, then go through removing process by process until you find the offending code.
You are also using an outdated version of Vivado (>2 years old). Any chance you could update to 2019.2?
I updated to Vivado 2019 and still have the same problem.
 

MSAKARIM

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I found this " An unexpected error has occurred (EXCEPTION_ACCESS_VIOLATION) "

Note: Vivado synthesized all other files properly only this file failed ( although it works well in simulation mode and i have the desired result)

Code:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_arith.all;
USE IEEE.STD_LOGIC_unsigned.all;


ENTITY SBOX IS 
PORT (CLK,RST: IN STD_LOGIC;
       SI: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
       SO: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END SBOX;

ARCHITECTURE SBOX OF SBOX IS
--COMPONENTS--
COMPONENT M1 is
port (a,b,c,d:in std_logic;
     Y: out std_logic_vector(7 downto 0));
end COMPONENT;
COMPONENT M2 is
port (a,b,c,d:in std_logic;
     Y: out std_logic_vector(7 downto 0));
end COMPONENT;
COMPONENT M3 is
port (a,b,c,d:in std_logic;
     Y: out std_logic_vector(7 downto 0));
end COMPONENT;
COMPONENT M4 is
port (a,b,c,d:in std_logic;
     Y: out std_logic_vector(7 downto 0));
end COMPONENT;
COMPONENT M5 is
port (a,b,c,d:in std_logic;
     Y: out std_logic_vector(7 downto 0));
end COMPONENT;
COMPONENT M6 is
port (a,b,c,d:in std_logic;
     Y: out std_logic_vector(7 downto 0));
end COMPONENT;
COMPONENT M7 is
port (a,b,c,d:in std_logic;
     Y: out std_logic_vector(7 downto 0));
end COMPONENT;
COMPONENT M8 is
port (a,b,c,d:in std_logic;
     Y: out std_logic_vector(7 downto 0));
end COMPONENT;
COMPONENT M9 is
port (a,b,c,d:in std_logic;
     Y: out std_logic_vector(7 downto 0));
end COMPONENT;
COMPONENT M10 is
port (a,b,c,d:in std_logic;
     Y: out std_logic_vector(7 downto 0));
end COMPONENT;
COMPONENT M11 is
port (a,b,c,d:in std_logic;
     Y: out std_logic_vector(7 downto 0));
end COMPONENT;
COMPONENT M12 is
port (a,b,c,d:in std_logic;
     Y: out std_logic_vector(7 downto 0));
end COMPONENT;
COMPONENT M13 is
port (a,b,c,d:in std_logic;
     Y: out std_logic_vector(7 downto 0));
end COMPONENT;
COMPONENT M14 is
port (a,b,c,d:in std_logic;
     Y: out std_logic_vector(7 downto 0));
end COMPONENT;
COMPONENT M15 is
port (a,b,c,d:in std_logic;
     Y: out std_logic_vector(7 downto 0));
end COMPONENT;
COMPONENT M16 is
port (a,b,c,d:in std_logic;
     Y: out std_logic_vector(7 downto 0));
end COMPONENT;
COMPONENT MUX1 IS
PORT(A0,A1,A2,A3: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
     D,C: IN STD_LOGIC;
     OUT1: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END COMPONENT;
COMPONENT REG4 IS
PORT ( CLK,RST: IN STD_LOGIC;
          A: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
          B: OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END COMPONENT;
COMPONENT REG8 IS
PORT ( CLK,RST: IN STD_LOGIC;
          A: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
          B: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END COMPONENT;

--SIGNALS--
SIGNAL AREG4,BREG4: STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL M1OUT, M2OUT,M3OUT,M4OUT,M5OUT,M6OUT,M7OUT,M8OUT,M9OUT,M10OUT,M11OUT,M12OUT,M13OUT,M14OUT,M15OUT,M16OUT,MXOUT1,MXOUT2,MXOUT3,MXOUT4,MXOUT5,REG80,REG81,REG82,REG83 : STD_LOGIC_VECTOR (7 DOWNTO 0);
sIGNAL  MM1OUT, MM2OUT,MM3OUT,MM4OUT,MM5OUT,MM6OUT,MM7OUT,MM8OUT,MM9OUT,MM10OUT,MM11OUT,MM12OUT,MM13OUT,MM14OUT,MM15OUT,MM16OUT : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN

AREG4 <= SI(3)&SI(2)&SI(1)&SI(0);



REG1: REG4 PORT MAP (CLK,RST,AREG4,BREG4);

MA1: M1 PORT MAP (BREG4(3),BREG4(2),BREG4(1),BREG4(0),M1OUT);
MA2: M2 PORT MAP (BREG4(3),BREG4(2),BREG4(1),BREG4(0),M2OUT);
MA3: M3 PORT MAP (BREG4(3),BREG4(2),BREG4(1),BREG4(0),M3OUT);
MA4: M4 PORT MAP (BREG4(3),BREG4(2),BREG4(1),BREG4(0),M4OUT);
MA5: M5 PORT MAP (BREG4(3),BREG4(2),BREG4(1),BREG4(0),M5OUT);
MA6: M6 PORT MAP (BREG4(3),BREG4(2),BREG4(1),BREG4(0),M6OUT);
MA7: M7 PORT MAP (BREG4(3),BREG4(2),BREG4(1),BREG4(0),M7OUT);
MA8: M8 PORT MAP (BREG4(3),BREG4(2),BREG4(1),BREG4(0),M8OUT);
MA9: M9 PORT MAP (BREG4(3),BREG4(2),BREG4(1),BREG4(0),M9OUT);
MA10: M10 PORT MAP (BREG4(3),BREG4(2),BREG4(1),BREG4(0),M10OUT);
MA11: M11 PORT MAP (BREG4(3),BREG4(2),BREG4(1),BREG4(0),M11OUT);
MA12: M12 PORT MAP (BREG4(3),BREG4(2),BREG4(1),BREG4(0),M12OUT);
MA13: M13 PORT MAP (BREG4(3),BREG4(2),BREG4(1),BREG4(0),M13OUT);
MA14: M14 PORT MAP (BREG4(3),BREG4(2),BREG4(1),BREG4(0),M14OUT);
MA15: M15 PORT MAP (BREG4(3),BREG4(2),BREG4(1),BREG4(0),M15OUT);
MA16: M16 PORT MAP (BREG4(3),BREG4(2),BREG4(1),BREG4(0),M16OUT);

BeforeMUX1: REG8 PORT MAP (CLK,RST,M1OUT, MM1OUT);
BeforeMUX2: REG8 PORT MAP (CLK,RST,M2OUT,  MM2OUT);
BeforeMUX3: REG8 PORT MAP (CLK,RST,M3OUT,  MM3OUT);
BeforeMUX4: REG8 PORT MAP (CLK,RST,M4OUT,  MM4OUT);
BeforeMUX5: REG8 PORT MAP (CLK,RST,M5OUT,  MM5OUT);
BeforeMUX6: REG8 PORT MAP (CLK,RST,M6OUT,  MM6OUT);
BeforeMUX7: REG8 PORT MAP (CLK,RST,M7OUT,  MM7OUT);
BeforeMUX8: REG8 PORT MAP (CLK,RST,M8OUT,  MM8OUT);
BeforeMUX9: REG8 PORT MAP (CLK,RST,M9OUT,  MM9OUT);
BeforeMUX10: REG8 PORT MAP (CLK,RST,M10OUT,  MM10OUT);
BeforeMUX11: REG8 PORT MAP (CLK,RST,M11OUT,  MM11OUT);
BeforeMUX12: REG8 PORT MAP (CLK,RST,M12OUT,  MM12OUT);
BeforeMUX13: REG8 PORT MAP (CLK,RST,M13OUT,  MM13OUT);
BeforeMUX14: REG8 PORT MAP (CLK,RST,M14OUT,  MM14OUT);
BeforeMUX15: REG8 PORT MAP (CLK,RST,M15OUT,  MM15OUT);
BeforeMUX16: REG8 PORT MAP (CLK,RST,M16OUT,  MM16OUT);



MX1: MUX1 PORT MAP (MM1OUT,MM2OUT,MM3OUT,MM4OUT, SI(5),SI(4),MXOUT1);
MX2: MUX1 PORT MAP (MM5OUT,MM6OUT,MM7OUT,MM8OUT, SI(5),SI(4),MXOUT2);
MX3: MUX1 PORT MAP (MM9OUT,MM10OUT,MM11OUT,MM12OUT, SI(5),SI(4),MXOUT3);
MX4: MUX1 PORT MAP (MM13OUT,MM14OUT,MM15OUT,MM16OUT, SI(5),SI(4),MXOUT4);

AREG8: REG8 PORT MAP (CLK,RST,MXOUT1, REG80);
BREG8: REG8 PORT MAP (CLK,RST,MXOUT2, REG81);
CREG8: REG8 PORT MAP (CLK,RST,MXOUT3, REG82);
DREG8: REG8 PORT MAP (CLK,RST,MXOUT4, REG83);

MX5: MUX1 PORT MAP (REG80,REG81,REG82,REG83,SI(7),SI(6),MXOUT5);

EREG8: REG8 PORT MAP (CLK,RST,MXOUT5,SO);



END SBOX;
All sub-modules are synthesized well and i have no syntax error,
when i google this issue i found this:" https://www.xilinx.com/support/answers/66106.html " , but i dont know how to apply it
I resolved this issue and i want to share the solution if any one has a similar issue.
I commented all code, then remove commenting blocks one by one till i reached to the block which causes this issue ( in Line):

Code:
MX1: MUX1 PORT MAP (MM1OUT,MM2OUT,MM3OUT,MM4OUT, SI(5),SI(4),MXOUT1);
i just renamed its entity and IT WORKS!
 

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