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Vivado simulation variables

Mustaine

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Hello friends i am currently studying the Digital Design by morris mano and when i set the example below to the vivado screen i cannot attain the state variables. How can i do that can you hrlp me about that
thanks in advance.
 

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niciki

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First of all check this quick take from Xilinx about Logic Simulator:

Select scope from scopes window (e.g. Mealy_Zero_Detector) then drag and drop your signals to waveform window:
1618345652124.png


By the way - your state/next_state are not variables.
 

dpaul

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Hello friends i am currently studying the Digital Design by morris mano and when i set the example below to the vivado screen i cannot attain the state variables.
Now I understand why some of the Newbies still use the two process method for state-machines.

How can i do that can you hrlp me about that
I also do not see any variables in the posted code.
 

Mustaine

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First of all check this quick take from Xilinx about Logic Simulator:

Select scope from scopes window (e.g. Mealy_Zero_Detector) then drag and drop your signals to waveform window:
View attachment 168812

By the way - your state/next_state are not variables.
thanks it helped a lot and why did you said that they are not variables.
 

niciki

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Regarding "state/next_state are not variables"... Surprisingly for me - they really are variables in a Verilog context!

This is surprise for me, because in VHDL (I am more experienced with VHDL) the variable is only used in a process, procedure or in function using variable keyword (as described here).

In Verilog there is a similar keyword var, but going into details of IEEE specifications of Verilog, which according to https://en.wikipedia.org/wiki/Verilog:
In 2009, the Verilog standard (IEEE 1364-2005) was merged into the SystemVerilog standard, creating IEEE Standard 1800-2009. Since then, Verilog is officially part of the SystemVerilog language. The current version is IEEE standard 1800-2017.
I've checked IEEE Std 1800-2017 and it says:
There are two main groups of data objects: variables and nets. These two groups differ in the way in which they are assigned and hold values.
Variables can be written by one or more procedural statements, including procedural continuous assignments. The last write determines the value. Alternatively, variables can be written by one continuous assignment or one port.
So any data object that is not a net, is defined as a variable. That means state and next_state are variables:

Code Verilog - [expand]
1
reg [1: 0] state, next_state;


I made a rash statement - I apologise.

Nevertheless IMHO this definition of a variable can be misleading for a software guy, who wants to start a journey with the FPGA using Verilog.
 
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Mustaine

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Regarding "state/next_state are not variables"... Surprisingly for me - they really are variables in a Verilog context!

This is surprise for me, because in VHDL (I am more experienced with VHDL) the variable is only used in a process, procedure or in function using variable keyword (as described here).

In Verilog there is a similar keyword var, but going into details of IEEE specifications of Verilog, which according to https://en.wikipedia.org/wiki/Verilog:

I've checked IEEE Std 1800-2017 and it says:


So any data object that is not a net, is defined as a variable. That means state and next_state are variables:

Code Verilog - [expand]
1
reg [1: 0] state, next_state;


I made a rash statement - I apologise.

Nevertheless IMHO this definition of a variable can be misleading for a software guy, who wants to start a journey with the FPGA using Verilog.
i got the point. Thanks for your detailed answer.
 

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