Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 entity TV is Port ( clk : in STD_LOGIC; en : in STD_LOGIC; rst : in STD_LOGIC; q : out STD_LOGIC_VECTOR (0 to 7)); end TV; architecture Behavioral of TV is component dff is Port ( d : in STD_LOGIC; clk : in STD_LOGIC; rst : in STD_LOGIC; q : out STD_LOGIC); end component; attribute keep : string; signal d:std_logic_vector(0 to 7); attribute keep of d : signal is "true"; begin l1: dff port map (d(0),clk,rst,q(0)); d(0)<= clk and en; l2:dff port map (d(1),clk,rst,q(1)); d(1)<= d(0) and en; l3:dff port map (d(2),clk,rst,q(2)); d(2)<= d(1) and en; l4:dff port map (d(3),clk,rst,q(3)); d(3)<= d(2) and en; l5:dff port map (d(4),clk,rst,q(4)); d(4)<= d(3) and en; l6:dff port map (d(5),clk,rst,q(5)); d(5)<= d(4) and en; l7:dff port map (d(6),clk,rst,q(6)); d(6)<= d(5) and en; l8:dff port map (d(7),clk,rst,q(7)); d(7)<= d(6) and en; end Behavioral;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY tb IS END tb; ARCHITECTURE behavior OF tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT TV PORT( clk : IN std_logic; en : IN std_logic; rst : IN std_logic; q : OUT std_logic_vector(0 to 7) ); END COMPONENT; --Inputs signal clk : std_logic := '0'; signal en : std_logic := '0'; signal rst : std_logic := '1'; --Outputs signal q : std_logic_vector(0 to 7); -- Clock period definitions constant clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: TV PORT MAP ( clk => clk, en => en, rst => rst, q => q ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 100 ns; rst<='0'; en<='1'; wait for clk_period*10; -- insert stimulus here wait; end process; END;
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+-----+------+
| |Cell |Count |
+------+-----+------+
|1 |BUFG | 1|
|2 |LUT2 | 8|
|3 |FDRE | 8|
|4 |IBUF | 3|
|5 |OBUF | 8|
+------+-----+------+
Report Instance Areas:
+------+---------+-------+------+
| |Instance |Module |Cells |
+------+---------+-------+------+
|1 |top | | 28|
|2 | l1 |dff | 1|
|3 | l2 |dff_0 | 1|
|4 | l3 |dff_1 | 1|
|5 | l4 |dff_2 | 1|
|6 | l5 |dff_3 | 1|
|7 | l6 |dff_4 | 1|
|8 | l7 |dff_5 | 1|
|9 | l8 |dff_6 | 1|
+------+---------+-------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:20 ; elapsed = 00:00:31 . Memory (MB): peak = 466.059 ; gain = 259.000
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 466.059 ; gain = 239.672
Synthesis Optimization Complete : Time (s): cpu = 00:00:20 ; elapsed = 00:00:31 . Memory (MB): peak = 466.059 ; gain = 259.000
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
INFO: [Common 17-83] Releasing license: Synthesis
22 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 564.609 ; gain = 340.313
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 564.609 ; gain = 0.000
INFO: [Common 17-206] Exiting Vivado at Wed Jul 03 00:12:58 2019...
I’m not going to unzip your file, but where is your component “diff”? Is it properly included in your project?
That's doesn't look like the complete synth log file.
Look into project_name.runs/synth_1/runme.log
Your synth log says there are no timing constraints for your design.
What are you trying to do?
Timing constraints have nothing to do with the visibility of signals in simulation.Your synth log says there are no timing constraints for your design.
What are you trying to do?
The OP finds a mismatch b/w func sim & post-impl sim. I found out he has no constraints file and still performing post-impl sim. Is it correct to perform a synth & pst-impl sim without design constraints?Timing constraints have nothing to do with the visibility of signals in simulation.
The OP finds a mismatch b/w func sim & post-impl sim. I found out he has no constraints file and still performing post-impl sim. Is it correct to perform a synth & pst-impl sim without design constraints?
Code VHDL - [expand] 1 2 3 4 5 6 7 8 d(0)<= clk and en; d(1)<= d(0) and en; d(2)<= d(1) and en; d(3)<= d(2) and en; d(4)<= d(3) and en; d(5)<= d(4) and en; d(6)<= d(5) and en; d(7)<= d(6) and en;
Code VHDL - [expand] 1 2 3 4 5 6 d(0) <= clk and en; -- d(0) d(1) <= (clk and en) and en; -- d(1) d(2) <= (clk and en and en) and en; --...
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