wtr
Full Member level 5

Hello all,
Unfortunately the work is company_ip/classified so I can't post it all however let me briefly describe the following design.
I have a pretty elaborate clocking scheme.
20MHz in to MMCM_1 which generates 100MHZ, 50MHz, 20MHz & clock_lock(global reset) out.
100Mhz & unique_timed_reset into MMCM_2 which generates 300MHz & clock_lock1
100MHz & unique_timed_reset2 into MMCM_3 which generates 64MHz & clock_lock2
64MHz & unique_timed_reset3 into MMCM_4 which generates 40.9MHz & clock_lock_3.
This results in a sequenced start up. The syntax would look something like
Constraints used
create_clock -period 50.000 -name clk_in_to_sysclk [get_ports clk_in]
..some jitter constraint.
This is the only timing constraint I specify. The MMCM is instantiated in RTL & therefore Xilinx does not have the xci ip generated xdc's.
Previously I set_false_paths & my firmware worked on 3/4 boards, & 4/4 when rerouted....yet fails thermal.
Internally I deal with cdc as can be seen by the S_drive_we being retimed.
Below is an example of the one hold WHS error I'm getting. I have an block which uses the 20Mhz clock domain & the 100Mhz clock domain.
I know it's bad practices to use the clock tree. However I don't know how to assign the clk20mhz_reg without sampling the clk20mhz.
Anyway, long story short, after all this I get a hold warning, where
from ../MMCM_1/clkout2(20mhz) to ../../some_entity/clk20mhz_reg
results in -0.620 slack
Unfortunately the work is company_ip/classified so I can't post it all however let me briefly describe the following design.
I have a pretty elaborate clocking scheme.
20MHz in to MMCM_1 which generates 100MHZ, 50MHz, 20MHz & clock_lock(global reset) out.
100Mhz & unique_timed_reset into MMCM_2 which generates 300MHz & clock_lock1
100MHz & unique_timed_reset2 into MMCM_3 which generates 64MHz & clock_lock2
64MHz & unique_timed_reset3 into MMCM_4 which generates 40.9MHz & clock_lock_3.
This results in a sequenced start up. The syntax would look something like
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 clk_in_ibuf : IBUF port map (I => clk_in, o => clk_in1); mmcm_1 : mmcme2_adv generic map(... blah..) port map(... blah... clkin => clk_in1, clkout0 => clk100mhz, clkout1 => clk50mhz, clkout2 => clk20mhz); mmcm_2 : mmcme2_adv generic map(... blah..) port map(... blah... clkin => clk100mhz, clkout0 => clk300mhz); --etc
Constraints used
create_clock -period 50.000 -name clk_in_to_sysclk [get_ports clk_in]
..some jitter constraint.
This is the only timing constraint I specify. The MMCM is instantiated in RTL & therefore Xilinx does not have the xci ip generated xdc's.
Previously I set_false_paths & my firmware worked on 3/4 boards, & 4/4 when rerouted....yet fails thermal.
Internally I deal with cdc as can be seen by the S_drive_we being retimed.
Below is an example of the one hold WHS error I'm getting. I have an block which uses the 20Mhz clock domain & the 100Mhz clock domain.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 some_entity : blah port map (clk100mhz => clk100mhz, clk20mhz => clk20mhz ..blah); -- within there is a section where I try to detect falling edge if rising_edge(clk100mhz) then if clk20mhz_old='1' and clk20mhz_reg='0' and drive_we='1' then data_to_drive_we <='1'; else data_to_drive_we <='0'; end if clk20mhz_reg <= clk20mhz; clk20mhz_old <= clk20mhz_reg; drive_we <= s_drive_we; --where s_drive_we was assigned in 20mhz domain. end if; end process;
I know it's bad practices to use the clock tree. However I don't know how to assign the clk20mhz_reg without sampling the clk20mhz.
Anyway, long story short, after all this I get a hold warning, where
from ../MMCM_1/clkout2(20mhz) to ../../some_entity/clk20mhz_reg
results in -0.620 slack