Viterbi Decoding Help

[Abhijith Yadav]

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity viterbi_count is
port (enc_data:in std_logic_vector(1 downto 0);
dec_dataut std_logic_vector(7 downto 0);
test ut std_logic_vector(7 downto 0);
clock : in std_logic);
end viterbi_count;

architecture decode of viterbi_count is
type previous is array( 1 downto 0) of std_logic_vector(1 downto 0);
type outputs is array(1 downto 0) of std_logic_vector(1 downto 0);
type paths is array(1 downto 0)of std_logic_vector(7 downto 0);
type metrics is array(1 downto 0) of integer range 0 to 17;
type table_record is
record
out_enc : outputs;
temp_pathsaths;
finalpath:std_logic_vector(7 downto 0);
statemetrics:metrics;
statemetric:integer range 0 to 17;
end record;
signal A:table_record;
signal B:table_record;
signal C:table_record;
signal D:table_record;
signal ct: integer range 0 to 8;
signal path_decide: std_logic_vector(7 downto 0);
signal metric_decide: integer range 0 to 16;
begin
A.out_enc<=("11","00");
B.out_enc<=("01","10");
C.out_enc<=("00","11");
D.out_enc<=("10","01");
process(clock,enc_data,ct,A,B,C,D)
begin
if(rising_edge(clock)) then
ct<=ct+1;
if(ct=1) then
A.finalpath<="00000000";
C.finalpath<="00000001";
for i in 0 to 1 loop
if(A.out_enc(0)(i)/=enc_data(i)) then
A.statemetric<=A.statemetric+1;
end if;
if(C.out_enc(0)(i)/=enc_data(i)) then
C.statemetric<=C.statemetric+1;
end if;
end loop;
end if;
if(ct=2) then
A.finalpath<="00000000";
B.finalpath<="00000010";
C.finalpath<="00000001";
D.finalpath<="00000011";
for i in 0 to 1 loop
if(A.out_enc(0)(i)/=enc_data(i)) then
A.statemetric<=A.statemetric+1;
end if;
if(B.out_enc(0)(i)/=enc_data(i)) then
B.statemetric<=C.statemetric+1;
end if;
if(D.out_enc(0)(i)/=enc_data(i)) then
D.statemetric<=C.statemetric+1;
end if;
if(C.out_enc(0)(i)/=enc_data(i)) then
C.statemetric<=A.statemetric+1;
end if;
end loop;
A.temp_paths<=(B.finalpath,A.finalpath);
B.temp_paths<=(D.finalpath,C.finalpath);
C.temp_paths<=(B.finalpath,A.finalpath);
D.temp_paths<=(D.finalpath,C.finalpath);
A.statemetrics<=(B.statemetric,A.statemetric);
B.statemetrics<=(D.statemetric,C.statemetric);
C.statemetrics<=(B.statemetric,A.statemetric);
D.statemetrics<=(D.statemetric,C.statemetric);
test<=A.temp_paths(0);
end if;
if(ct>2) then
if(enc_data="00") then
A.statemetrics(1)<=A.statemetrics(1)+2;
B.statemetrics(0)<=B.statemetrics(0)+1;
B.statemetrics(1)<=B.statemetrics(1)+1;
C.statemetrics(0)<=C.statemetrics(0)+2;
D.statemetrics(0)<=A.statemetrics(0)+1;
D.statemetrics(1)<=A.statemetrics(1)+1;
end if;
if(enc_data="01") then
A.statemetrics(0)<=A.statemetrics(1)+1;
A.statemetrics(1)<=B.statemetrics(0)+1;
B.statemetrics(0)<=B.statemetrics(1)+2;
C.statemetrics(0)<=C.statemetrics(0)+1;
C.statemetrics(1)<=A.statemetrics(0)+1;
D.statemetrics(1)<=A.statemetrics(1)+2;
end if;
if(enc_data="10") then
A.statemetrics(0)<=A.statemetrics(0)+1;
A.statemetrics(1)<=A.statemetrics(1)+1;
B.statemetrics(1)<=B.statemetrics(1)+2;
C.statemetrics(0)<=C.statemetrics(0)+1;
C.statemetrics(1)<=A.statemetrics(1)+1;
D.statemetrics(0)<=A.statemetrics(0)+2;
end if;
if(enc_data="11") then
A.statemetrics(0)<=A.statemetrics(0)+2;
B.statemetrics(0)<=B.statemetrics(0)+1;
B.statemetrics(1)<=B.statemetrics(1)+1;
C.statemetrics(1)<=C.statemetrics(1)+2;
D.statemetrics(0)<=A.statemetrics(0)+1;
D.statemetrics(1)<=A.statemetrics(1)+1;
end if;
if(A.statemetrics(0)<A.statemetrics(1)) then
A.statemetric<=A.statemetrics(0);
A.finalpath(7 downto 0)<=A.temp_paths(0)(6 downto 0)&'0';
else
A.statemetric<=A.statemetrics(1);
A.finalpath(7 downto 0)<=A.temp_paths(1)(6 downto 0)&'0';
end if;
if(B.statemetrics(0)<B.statemetrics(1)) then
B.statemetric<=B.statemetrics(0);
B.finalpath(7 downto 0)<=B.temp_paths(0)(6 downto 0)&'0';
else
B.statemetric<=B.statemetrics(1);
B.finalpath(7 downto 0)<=B.temp_paths(1)(6 downto 0)&'0';
end if;
if(C.statemetrics(0)<C.statemetrics(1)) then
C.statemetric<=C.statemetrics(0);
C.finalpath(7 downto 0)<=C.temp_paths(0)(6 downto 0)&'1';
else
C.statemetric<=C.statemetrics(1);
C.finalpath(7 downto 0)<=C.temp_paths(1)(6 downto 0)&'1';
end if;
if(D.statemetrics(0)<D.statemetrics(1)) then
D.statemetric<=D.statemetrics(0);
D.finalpath(7 downto 0)<=D.temp_paths(0)(6 downto 0)&'1';
else
D.statemetric<=D.statemetrics(1);
D.finalpath(7 downto 0)<=D.temp_paths(1)(6 downto 0)&'1';
end if;
A.temp_paths<=(B.finalpath,A.finalpath);
B.temp_paths<=(D.finalpath,C.finalpath);
C.temp_paths<=(B.finalpath,A.finalpath);
D.temp_paths<=(D.finalpath,C.finalpath);
A.statemetrics<=(B.statemetric,A.statemetric);
B.statemetrics<=(D.statemetric,C.statemetric);
C.statemetrics<=(B.statemetric,A.statemetric);
D.statemetrics<=(D.statemetric,C.statemetric);
end if;
if(ct=8) then
ct<=0;
path_decide<=A.finalpath;
metric_decide<=A.statemetric;
if(B.statemetric<metric_decide) then
path_decide<=B.finalpath;
metric_decide<=B.statemetric;
end if;
if(C.statemetric<metric_decide) then
path_decide<=C.finalpath;
metric_decide<=C.statemetric;
end if;
if(D.statemetric<metric_decide) then
path_decide<=D.finalpath;
metric_decide<=D.statemetric;
end if;
dec_data<=path_decide;
A.statemetrics<=(0,0);
B.statemetrics<=(0,0);
C.statemetrics<=(0,0);
D.statemetrics<=(0,0);
A.statemetric<=0;
B.statemetric<=0;
C.statemetric<=0;
D.statemetric<=0;
end if;
end if;
end process;
end decode;

- - - Updated - - -

The above is my code for Viterbi decoder for k=3 r=0.5. It has no undesired warnings.... But the output I observed thjrough wave from file is wrong... The logic is that the first two cycles, the incoming data(enc_data is ) is jus compared ad required set of pre defined actions on various parameters are done. After the frst two cycles, the enc_data is checked for it being 00,01,10,11 and corresponding metics are only played with. Then depending on the branch metrics at one state, path decision in each clock cycle is taken. Tell me if I have done something wrong here

 

[mrflibble]

Can you show us the testbench + results?

 

[Abhijith Yadav]

i did not test bench it.. because i dunnno how to do it. i will post the simulation results though..( vector wavefrorm file)

 

[TrickyDicky]

i did not test bench it.. because i dunnno how to do it. i will post the simulation results though..( vector wavefrorm file)

I suggest you read up on how to write a testbench then....