Viterbi decoder (modern technology)

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Djony1987

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Hi,
In my final project i design some digital communication system (BPSK, DSSS, concatenated coding(Convolutional(K=7, r=1/2) + Reed-Solomon(255,239)) and so on...)

Now i need to design Viterbi decoder...what technology i can use? Technology, related with low power and low area on chip.

There are so many articles in internet, it's hard to choose optimal technology for every block of Viterbi decoder, like ACS, BMC ans so on...

Thank!
 

you can use radix-4 algorithm for viterbi decoder. this will double the throughput of your system.But if you dont want such high throughput then design a sst viterbi decoder.This kind of decoder is for low power consumption.
Remember that for both of the above designs are made for improvising the viterbi decoder throughput or efficiency.First you have to design a basic viterbi decoder using "traceback architecture" or "Register exchange archi"..

the specific design arch depends on your requirements. first decide whether you need a low power design or low resource design or a high throughput design.

--vipin
https://vhdlguru.blogspot.com/
 

vipinlal, thank! Choose traceback with 2 ACS (32 iteration).
 

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