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viterbi decoder in vhdl code

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setareh_mehr85

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vhdl decoder

could any one help to write my code in vhdl for viterbi decoder 1/2 rate with constraint length 3 I did some coding for a start but I'm not sure is it correct or not

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

entity generatorcode is

port(
clk : in std_logic;
reset : out std_logic;
encoder : in std_logic;
data : in std_logic
);


end generatorcode;
 

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