viterbi 7.0 decoder not generating output data

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Harshit29

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Hi Friends I am using viterbi decoder 7.0 with punctured data rate of 3/4.

I depunctured data and also generated erase signal according to the IP datasheet but i am not getting output can anyone tell me how to solve it?
 

Harshit29 said:
Hi Friends I am using viterbi decoder 7.0 with punctured data rate of 3/4.

I depunctured data and also generated erase signal according to the IP datasheet but i am not getting output can anyone tell me how to solve it?
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By debugging?

Nobody here can debug it, we don't have your PC with the code and environment you have, besides you don't even mention which vendor's decoder you are using.

Do you have a testbench?
Did you run the simulation?
If there is any HDL code produced by the IP generation did you trace the output back through the simulation?
Do you have a clock?
Did it come out of reset, or is the polarity of the reset correct?

Or is this a case of generate IP, synthesis, place-n-route, download to FPGA, Oh, it doesn't work!
 

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