Virtuoso vs Design Compiler

[master_picengineer]

Hi all,
I have a questions that perhaps seems to you strange.
1- if I design for exemple a dff using Virtuoso and Design compiler (in 90 nm techn). What is the maximum frequency that can be reached for each one (Which one will be speeder) ?

2- Why front end design still necessary in design flow since all that we can do using design compiler can be directly and easyli be done using Virtuoso.
In fact, it's library is richer, its silulation result is closer to reality and it encopasses analog and digital standard cells (PLL, VCO, DFF, ...).

Thanks in advance.

 

[hung_wai_ming@hotmail.com]

Virtuoso is a platform for analog circuit design, schematic capture, layout editor, or simulation

Design complier is a tool for RTL synthesis.

They are TOTALLY two different sets of tools when uses both, is a mixed signal design system

All librarys from design compiler are actually done each by each from schematic and layout.

I doubt if you really understand what is design compiler?

Did u do RTL before?

 

[master_picengineer]

Hi,
In fact I'am familiar in front end and new in back end/ Analog design. I'm a new user of Virtuoso.
My actual work is to design high speed devices (2 to 6) GHz, these frequency can not be reached using Front end tools like Design compiler. For exemple, in 65 nm the max clock frequency of a dFF is 1 Ghz. I was obliged to go down (perhaps to transistor level) and redesign my device using Virtuoso but I'm not sure so far if it give better result or not.

 

[hung_wai_ming@hotmail.com]

master_picengineer

I think for whole chip functionally, you should work on RTL, as baseband processing is usually done in RTL, as you know it.
For particular device that requires high frequency as your need, you need to sort for custom design as typical library did not provide such a high speed dff, since typical dff is master/slave type while high speed usually TSPC or dynamic logic type, therefore speed tends to be much faster.

However, I would recommend you find a real analog design to do it, as in the first time, you would have lots of simple problems and errors and it is not worthwhile you do it on your own.

 

[master_picengineer]

Thanks friend,
I heard about the High speed library but I didn't use it. Could you please through more ligth on HS dff.
What do you mean with TSPC and dynamic logic ?
Is there any document for basics information ?

Regards,
master_picengineer

 

[hung_wai_ming@hotmail.com]

I think any one of the CMOS digital circuit books will talk about TSPC and implementation of DFF using TSPC. You may also search Phase Frequency Detector in PLL design and there also uses TSPC DFF as well. If not you can find, just tell me

 

[master_picengineer]

Hi hung_wai_ming@hotmail.com,
I tried to find documentation on this issue, unfortunately I coudn't find books on TPSC.
Can you tell me some books titles/autors.
Please If you have some docs share it. I'll be very greatefull.
Thanks in advance.

 

[jasonxilion]

here is a pic about the tpsc

 

[layes2]

DC for syn
VIRTUSO for custom ic design