Virtual clock vs Real clock

[kpsr]

Hi Folks,

I need small help regarding virtual clock and real clock

Question ::

If I define two different clock periods for virtual clock and real clock what are effects we can see in design

Ex :: virtual clock is vclk 1000ps
Real clock is 1500ps

What type of effects we can see in design asked by one interviewer.

Please let me know the answer as soon as possible.

Thanks in advance,
kpsr.

 

[rca]

virtual clock, there is no source pin defined. real clock there is a source pin defined, that only the difference. Then during CTS, the virtual clock is not balanced.
And the virtual clock could be used to describe the behavior of I/O, I mean to indicate the I/O moves is two slower than the real clocks, and if you have properly define the various edge, for the virtual and real clocks, the synthesiser will now the margin he have, on this I/O.

 

[kpsr]

Thanks rca,

If we define virtual clock is vclk 1000ps Real clock is 1500ps like this, Is there any effect on reg to reg path due to vclk.

 

[rca]

The virtual clock has no effect on reg 2 reg path, because , this clock has no source point then no registers impacted by this clock.
But if this clock is used to define set_input_delay or set_output_delay, this could impact the i2reg or reg2out, and in2out.