Virtex-IIP PowerPC Simulation

[mami_hacky]

any one has has any experiance with simulating a design, which uses Virtex-IIP's powerPC uProcessors?
Can any one describe me what are smart models, and what is SWIFT? and if I need Synopsys Model Compiler for my functional simulations?

 

[simon2kk]

As far as I know, the simulation for the embedded PowerPC core can be done using Virtex-II pro developer's kit.
It includes the swift model for the PowerPC and associated gnu gcc compiler.
You can simulate using Modelsim.
But, Xilinx is still developing the tool and is in alpha version.

Simon2kk

 

[mami_hacky]

Then can any one describe what is core connect? Do I need it to performe simulations?

 

[simon2kk]

CoreConnect is the bus standard from IBM.
In Xilinx tool, it is designed as Soft IP which means that it uses the CLB (or Slice in Virtex-II pro) on FPGA.
You can instantiate and simulate it for PowerPC core or MicroBlaze processors.

simon2k

 

[simon2kk]

Hello, mami_hacky.

I did not answer your question.
Regarding the question whether you have to use CoreConnect or not,
it is up to you.
CoreConnect is the optional bus for PowerPC and Microblaze.
If you need your own bus, you can design and use it on V-IIpro.
Of course, it is much easier to use an available bus like CoreConnect.

simon2kk

 

[Ohh]

SWIFT is a quasi-industy standard proposed by Synopsys about 10 years ago. Using SWIFT, IP developers can compile the HDL model of their IP cores into a binary (encrypted) model which can be simulated with other HDL models using HDL simulators that support SWIFT, e.g. ModelSim and many other tools.