Virtex 5, ml501, How to use Ethernet port?

[SUNBELT]

I am trying to use virtex 5 (ml501) for a mpeg decoder that I have recently downloaded. The video is supposed to be sent to the FPGA through Ethernet port.
These are the signals that are supposed to be connected to Ethernet:
output [3:0] TX_DATA_P; // Ethernet transmission data
output TX_ENABLE_P; // Ehternet transmission enable
input TX_CLOCK_P; // Ethernet transmission clock
input TX_ERROR_P; // Ethernet transmission error
output [1:0] ENET_SLEW_P; // Ethernet slew settings
input [3:0] RX_DATA_P; // Ethernet receive data
input RX_DATA_VALID_P; // Ethernet data valid
input RX_ERROR_P; // Ethernet receive error
input RX_CLOCK_P; // Ethernet receive clock
input COLLISION_DETECTED_P; // Ethernet collision detected
input CARRIER_SENSE_P; // Ethernet carrier sense
output PAUSE_P; // Ethernet pause
inout MDIO_P; // Ethernet config data
output MDC_P; // Ethernet config clock
input MDINIT_N; // Ethernet config init
inout SSN_DATA_P; // Silicon serial number access

How can I make sure that these pins are connected correctly to the Ethernet port. For example I know how to use plan ahead feature of the ISE (xilinx) to connect my input and output pins to my desired pins. But I am not sure how to do this for Ethernet port.

 

[permute]

some of these look like RMII/RGMII signals, some don't. In either case, ethernet on FPGA's uses a MAC+PHY system. I'm guessing that the mpeg core has an ethernet MAC, which really isn't the right thing to do. (now the interface is limited artificially)

The PHY is an external IC. The MDC/MDIO lines form a management interface for accessing the PHY's control functions. Not all PHY's have publically accessible datasheets, so advanced PHY features might be inaccessible to you. Usually, a dev board will be able to use dip switches to set basic PHY features. the 4b interface suggests a RMII/RGMII interface, but the CS/COL inputs suggest a MII/GMII input. You should probably see what the mpeg core expects.

The PHY can be set up for many different interfaces to the MAC on the FPGA. eg, MII, GMII, RGMII, SGMII, 1000BASE-X, TBI, RTBI. GMII is an 8b interface for Gbe, RGMII is a 4b DDR interface for Gbe, SGMII is a serial interface (uses GTP) for Gbe. MII is similar to GMII, but limited to 10/100.