Virtex 5, Arithmetic Functions, need some help and advice!

[Curtains]

Hey everyone

I have various functions, such as multiplying floatings points by floating points, i suppose i can use the given IPs, however there are cases where i need to power the floating point by ( 4 / 3 ) .

I have little experience in using DSP or Microblaze or any other Embedded processor within the FPGAs. I would say i am not familiar at all in using them.

So is that a direction i should be heading to ( DSP and microblaze ) ? or should i just rely on IPs given with ML501 chip?

Thanks

 

[allsey87]

A single division and exponent is no need to jump to using an embedded processor, the Virtex 5 should have plenty of DSP blocks that allow you to do this.

I would use an third party IP core, there is an open source project called FLoPoCo, it is a floating point core generator which allows you to type an expression which you want to calculate, and the software will automatically generate sythesisable VHDL code to match that expression.

I haven't used it before, but the project is quite active (last release was 2.5 weeks ago). The only thing I'm uncertain about it, is that I don't think it takes advantage of embedded multipliers or DSP blocks on the target platform - although this is not an issue for small designs.

Alternatively, you can draw your arithmetic function in simulink and then use 'simulink HDL coder' to generate the HDL for you, and this is target platform aware (i.e. it will take advantage of embedded multipliers and DSP blocks in the target FPGA)...

---------- Post added at 07:22 ---------- Previous post was at 07:17 ----------

**broken link removed**

 

[Curtains]

Thank you so much for the help.

I sounds pretty new, i just now have to read how to use the DSP blocks

 

[allsey87]

quick note there, it is unusual to use DSP block directly. the process is you infer them by writing certain operators in to your code in a certain way. you can read the XST guide for information on that.

based on the operator your trying to achieve, I would recommend you go for FloPoCo, installation is really easy if your running ubuntu...

ref: **broken link removed**

 

[TrickyDicky]

If you're doing floating point - just instantiate the floating point IP blocks.

 

[allsey87]

@TrickyDicky - Yeah I had a look at that, the coregen config for the FPU core in Xilinx doesn't have FP exponent function as an option. Hence why I suggest FloPoCo.

FloPoCo is really an amazing piece of software, can handle complex floating point exponentials, trig, as well as standard operators. The nice thing about it is one of the input modes, you just write the expression in a text file and it will generate an FPU with the required hardware to perform the operations in the given expression...

 

[mrflibble]

Hey allsey87, I did just take a look at FloPoCo. Looks interesting in principle. Is it also interesting in practice?

By which I mean to ask, is it practical and maintainable? Do you have any personal experiences with it's pros and cons? And specifically, do you know if it is any good for generating cores for sparse matrix multiplication?

 

[allsey87]

@mrfibble I have only considered using FloPoCo so far, but I can tell you that it doesn't take matrix operands and is developed for synthesis in FPGAs and ASICs.

FloPoCo generates FPU cores, which should not be modified or maintained, they should be treated as black boxes (unless of course you have read the 30 or so academic papers on the internals - then maybe you feel game enough to try to tweak it). If you need to change the core, then you would generally just regenerate it with the software...

I also haven't needed to work with Sparse matrices before, but matrix operations are generally standard FP operations done in a loops, so your steps to implement would be to figure out what operations you need, generate a core FloPoCo, design a FSM which distributes the data inside the blockram (or registers) which is the matrix elements...

 

[TrickyDicky]

The only concern with FloPoCo is that it may not be maintained in the long term, being a free to use 3rd party project. But if you only have short term goals, then have a play!

But just had a look at the developer manual. They use std_logic_unsigned/std_logic_arith. I heve less respect for projects like this that dont use standardised VHDL!

 

[allsey87]

Haha, yes I used to be like that too, anything other than numeric_std just wasn't good enough. after all std_logic_vector is a collection of bits, not necessarily a number!!

I'm a member of IEEE, and while I think numeric_std is the superior and better defined library, the truth is those libraries which everyone spits on with disgust (std_logic_unsigned/arith etc) have been placed there by industry leaders and are generally better in terms of optimisation during the synthesis process for FPGAs (I don't know about ASICs).

Understandably, if one isn't careful this can lead to confusing issues, but if your careful and aware of the traps of using std_logic_arith etc, they're actually not too bad, although I would still prefer to see synthesis tools support numeric_std. however, VHDL is slow to update... after all, how long have we been waiting for the VHDL 2008 standard to come in?

 

[TrickyDicky]

Afaik, all synthesis tools support numeric_std.
Plus VHDL 2008 has been released, and support is starting to appear (Quartus has some limited support, Modelsim 10.0 has nearlly full 2008 support).

 

[allsey87]

Yep, sorry that was a typo, Synthesis tools obviously support numeric_std, what I meant to say was its not optimised as well during synthesis. it is a short coming of tools like XST etc.

Interesting enough, while XST didn't appear to care whether I used numeric_std or not, the biggest trouble I ran into during development was trying to instantiate an instance of microblaze in my design with custom peripherals which had unsigned/signed ports...

Regarding VHDL2008, I'm talking about full synthesis support, simulation/implementation of a couple new lines of code is easy, once VHDL2008 is fully sythesisable, we would actually have FP data types match IEEE 754. although even then, we'll have to still wait along time before tools like XST are smart enough to not just support FP data types, but actually can implement them in a efficient way...

 

[mrflibble]

@mrfibble I have only considered using FloPoCo so far, but I can tell you that it doesn't take matrix operands and is developed for synthesis in FPGAs and ASICs.

FloPoCo generates FPU cores, which should not be modified or maintained, they should be treated as black boxes (unless of course you have read the 30 or so academic papers on the internals - then maybe you feel game enough to try to tweak it). If you need to change the core, then you would generally just regenerate it with the software...

Thank you for your reply! In my case it would get used for synthesis in fpga. But with regard to maintainability I did not mean as much "muck about inside the black box", but more how will this project be 1 year down the road? I see plenty of open source projects with good ideas & intentions, but after the first enthuasiasm induced few sprints it dies horribly. That sort of thing.

Other than that, if I were made of time, it looks like a fun thing to waste some time on. ;-)

I also haven't needed to work with Sparse matrices before, but matrix operations are generally standard FP operations done in a loops, so your steps to implement would be to figure out what operations you need, generate a core FloPoCo, design a FSM which distributes the data inside the blockram (or registers) which is the matrix elements...

What? Do the actual work *gasp* myself? And here I was thinking to use an abstraction layer to take care of that.

What I did like from the quick read I did was the support in FloPoCo for configurable pipelining. Right now what I do is basically instantiate primitives or core generator modules, and do the pipelining by hand. While this is fun of a certain sort and educational, it can get tedious after a while.

Also, reregistering in XST is either not that useful, or I need to read more stuff. For now I will just err on the side of caution, and do more reading... Which serves as a mild thread hijack for this question related to fpga implementation of larger math blocks... How do you manage your pipelines?