virtex-4 sx development boards

[chinsin83]

netlist is empty after trimming useless hardware

the ML402 evaluation platform does not include the development tools and cable.
i can find the price for the system generator, usd $995. wat else do i need?

the requirement for system generator is ISE v7.1 and MathWorks R14.1/.2/.3
it does not mean the ISE foundation rite? coz it cost usd $2495.

the video starter kit has the system generator included, do i need to get the ISE v7.1 or is it included? and what about the cable?

the XtremeDSP development board comes with the system generator at a higher price, but does it include the xtremedsp evaluation software, coz it have the ISE v7.1 .. or can i purchase the xtremedsp evaluation software separately for use with the ML402 evaluation platform?
https://www.xilinx.com/dsp/eval_software.htm

 

[echo47]

system generator netlist is empty

The Xilinx web pages are confusing, and I know only some of your answers.

I have an ML402 and ML403. Neither board included any software or documentation.

System Generator (about $1000 US) requires ISE Foundation (or the discontinued ISE Alliance), and it's not included. ISE Foundation costs about $2500 US. If you also want the EDK, that's another $500 US.

I don't use System Generator very much. I mostly use only ISE Foundation.

I don't know what is xtremedsp evaluation software.

I use the Xilinx Parallel Cable IV (about $100 US). It works with the ML40x boards, and the Spartan-3 Starter Kit, and probably most other Xilinx boards:
**broken link removed**
ISE Foundation (or the free ISE WebPACK) includes iMPACT, the cable download software.

 

[chinsin83]

thanks echo. really cleared my doubts alot.

btw, im doing at matlab level and not rtl level so i need the system generator.
the website also said that ISE alliance is sufficient, but there dun seem be a link to direct me to purchase the alliance seprately.

the first link stated that ise webpack do not support system generator but the 2nd link said that ise webpack 8.1i support it. lol .. think i have to wait for the release, but not sure how soon.
**broken link removed**
**broken link removed**

both system generator and ise foundation for evaluation comes with full features rite, or the evaluation comes with limited features? that way i can drag some time for ise webpack 8.1i and its free. ^.^

 

[samcheetah]

I don't use System Generator very much. I mostly use only ISE Foundation

do you think that sysgen is a useful tool. does it really simplify the MATLAB->RTL conversion process.

and the sysgen page at xilinx.com says that it has the microblaze core. so if i have sysgen, will that mean that i dont need EDK?

 

[chinsin83]

i've juz called the person in charge. he told me that system generator cannot convert m-codes to hdl. but here is a link that xilinx provide. does this mean i need to create my own m-code blocks in order for system generator to use?
https://www.xilinx.com/products/software/sysgen/app_docs/user_guide_Chapter_7_Section_3.htm

Added after 4 minutes:

juz found another link. does that mean if i wan to convert m-codes directly to FPGA, i need accelchip dsp synthesis tool also?
**broken link removed**

 

[echo47]

You did the right thing by asking your Xilinx sales rep. Their web page info is too skimpy.

System Generator doesn't compile M code. Instead, you draw a Simulink block diagram using the Xilinx blockset, and then press a button to generate a bitstream that you can download to your FPGA. That works fine if you use only high-level signal processing blocks (I think each block simply calls Xilinx CORE Generator), but I found it excruciatingly painful for creating sequencers and other miscellaneous logic. It's too much like schematic capture. A played with it for a day or two, and then went back to using HDL.

System Generator includes a MicroBlaze block symbol, but it doesn't seem to include any EDK functionality. That makes sense, because System Generator is about 20 megabytes, and EDK is gigabytes.

I haven't tried AccelChip, but I'm suspicious of any tool that claims to convert a high-level language to FPGA. The results are usually greatly inferior to hand-coded HDL. However, that may be acceptable if you have a small project and a big fast FPGA.

Xilinx discontinued ISE Alliance about a year ago. Customers with support agreements were automatically upgraded to ISE Foundation.

 

[samcheetah]

System Generator doesn't compile M code. Instead, you draw a Simulink block diagram using the Xilinx blockset, and then press a button to generate a bitstream that you can download to your FPGA. That works fine if you use only high-level signal processing blocks (I think each block simply calls Xilinx CORE Generator), but I found it excruciatingly painful for creating sequencers and other miscellaneous logic. It's too much like schematic capture. A played with it for a day or two, and then went back to using HDL.

im shocked!!!!!!!!!!!!

thanx for the info echo47

by the way, what design flow do you follow??

MATLAB -> C++ -> HDL

or

MATLAB -> HDL

i heard someone say that the first design flow is better but i dont see any benefit of first converting it into C++ and then into HDL.

 

[chinsin83]

found that my boss's boss have the ise foundation 7.1i, -,-" .. now trying out the system generator evaluation software. they have a mcode block which uses the function in m-file.

now im only trying out one function in one m-file, so my m-code block have the same i/o as my function. im not sure wat would happen if there are multiple function in one m-file.

now i need to input my dummy code into the fpga and see if i would get the same output ..

thanks echo .. hehe .. need more help will post here .. ^.^
good luck to u samcheetah ..

 

[echo47]

System Generator is not my cup of tea, but some folks like it. The evaluation is free, so give it a try. I consider it one tool in my toolbox. Someday it may save me a day of work, and it will pay for itself.

When I design signal processing systems, I do the high-level concept simulation in MATLAB m-code or C. MATLAB is easier unless I'm doing a lot of tricky binary manipulations, and that's easier in C. I don't use Simulink. My high-level simulation also spits out coefficient tables (in HDL format) for initializing block RAMs. Finally, I code the whole system in Verilog, test it with ModelSim, and compile to FPGA.


chinsin83, please let us know if that System Generator m-code block does anything useful for you. I guess I overlooked that key feature. Here's the online help introduction:

The Xilinx MCode block is a container for executing a user-supplied MATLAB function within Simulink. A parameter on the block specifies the m-code function name. The block executes the m-code to calculate block outputs during a Simulink simulation. The same code is translated in a straightforward way into equivalent behavioral VHDL when hardware is generated. The block's Simulink interface is derived from the MATLAB function signature, and from block mask parameters. There is one input port for each parameter to the function, and one output port for each value the function returns. Port names and ordering correspond to the names and ordering of parameters and return values.

The MCode block does not support the entire MATLAB language; the supported subset is described below. There are several noteworthy additional restrictions on the block and its usage:
- All block inputs and outputs must be of Xilinx fixed point type.
- The block must have at least one output port.
- The code for the block must exist on the MATLAB path or in the same directory as the model that uses the block.

This block provides a convenient and flexible way to implement arithmetic functions and to build finite state machines and control logic. The MCode block tutorial shows three examples of functions for the MCode block. The first example (also described below) consists of a function xlmax which returns the maximum of its inputs. The second illustrates how to do simple arithmetic. The third shows how to build finite state machines. The example models are linked from the Examples section of this guide.
<snip>

 

[chinsin83]

now i need to find the plug-in for the XESS XAS-3S1000 board which the XESS website does not provide .. duhz ...

any other way of installing my board for the hardware simulation?

 

[samcheetah]

now i need to find the plug-in for the XESS XAS-3S1000 board which the XESS website does not provide .. duhz ...

any other way of installing my board for the hardware simulation?

are you talking about downloading the code to the FPGA??? well, i think the XSA board requires a tool that is available on their site.

 

[chinsin83]

i think i read the manual wrongly .. now not really sure wat i wan .. going to read the manual again .. =(

Added after 1 hours 29 minutes:

i've used the System Generator Board Description Builder to create the plugin for my XESS XSA-3S1000 board .. when i used system generator to generate the block for simulink .. there's a error .. i think i specified the wrong system clock .. any1 have experienced with this board n can tell me which is the pin for the sytem clock?

 

[samcheetah]

i think you can easily find information about the clock from the manual. the XTAL should be connected to one of the GCKx pins. its always good to read the manual carefully.

 

[chinsin83]

hmm .. did a simple arithmetic function

constant input ----> HW co-sim block: input * 10 , output/ 2 ----> output displayed

hmm .. i run the simulation n it took like 10 secs for the display in my simulation to show me the value .. is it coz my board is lousy? -,- ..

btw .. how do i display an image if my board is connect to a monitor? ..
do i need to add in the pins for the vga port in my plug-in?

 

[samcheetah]

the simulation might be slow due to two reasons; one is that your computer is slow and the other is that your approach is not correct. your board being lousy is not an issue because you dont simulate on the board.

as for the vga. search on google with the keywords vga and fpga and you will get alot of useful info. and you should check the vga core at opencores.org

 

[chinsin83]

how do i calculate how much time the algorithms run in the fpga? ..

 

[FPGAs]

i think the xilinx FPGA boards aren't worth so much

 

[chinsin83]

er .. huh? ..

system generator for dsp 7.1i can support only some features of matlab functions, =( .. it cant even support 'for loop' ..

does any1 know how to include simulnk's blockset inside the configurable subsystem for system generator to import as configurable subsystem for the hw-co-simulation? ..

the xilinx block sets only accepts xilinx input .. so u have to use the gateway_in; but system generator cannot compile the gateway_in to be included in the hw-co-simulation.

 

[chinsin83]

hihi .. im back with new question ..

system generator's gateway cannot take in frame-based? .. then how do i simulate my data in hardware?..

if i din use xilinx's blockset .. can i still use the hardware co-simulation? .. coz when i click generate, theres an error specifying netlist is empty after trimming useless hardware. wat does that mean?