Video RAM: reading and writing?

Hi there,

I'm designing a VGA signal generator. I'm actually stuck into the design of the RAM interface. The RAM should contain the data that has to be put on the screen by the signal generator.

The signal generator requires (should it?) a continuous access to the RAM, this because the screen is continuously refreshed. As a consequence the address bus of that ram is constantly driven by the signal generator.
So, if my component continuously access to the RAM, keeping the address bus busy, how is one supposed to write data into that RAM?


Looking on the internet trying to find some examples I got this:


Looks like the device simply puts the desired address on TEXT_A and reads the corresponding data through TEXT_D. Ok, fair enough, but ...

How is it possible to write to the same RAM if this is being kept busy by that signal generator?
Does this requires a particular RAM (maybe with 2 separate pairs of buses) ?
Is it possible to interface this model (which requires a constant access to the RAM) with an external RAM like a DDR one?


Thank you for your time already.

Does your system works in this way?
A signal generator continuously writes data into the RAM.And at the same time data is read from the RAM to display it on the VGA.Is this what you want?
If this is your requirement then just use a dual port RAM.You can write and read the RAM at a different address and at the same time using a dual port RAM.If you are using Xilinx FPGA then core generator have IP cores available for RAM.

--vipin
https://vhdlguru.blogspot.com/

Yes vipinlal, that's it!

But what if someday I'll need more space and decide to switch to an external DDR RAM? Is there any way to obtain the same behavior from such a RAM? Or should I look for some other specific RAM ?

Thank you

you would then need to run the RAM at a suitable clock rate. you would need to be able to buffer small blocks of data on the FPGA, then perform memory accesses to the DDR.

You would need to schedule the memory accesses so that the combined read/write bandwidth was possible. the SRAMs would be sized such that enough data could be buffered to take into account the worst case turnaround time, and should probably be at least 1k elements large. That is because DDR takes a HUGE performance penalty when writing and reading different rows in the same bank.

Since you have to write 80*40 pixels for one screen doesnt mean that you need to store all of them in memory at a single time.What you can do is store the store 2 rows of pixels.This will take only 2*40 bytes of memory.
Now write the pixels(of first row) in first row initially and then write 2nd row of pixels in second row.Once first row is completely written you can start reading from it.By the time you start reading the 2nd row, the 3rd row from signal generator can be written into first row.

So, first row goes to first row in memory.
2nd row goes to 2nd row in memory.
3rd row goes to 1st row in memory.
4th goes to 2nd.
and 5th goes to 1st and so on...

read the memory using a demultiplexer.
1st row is read for first time.Then 2nd row is read.Then 1st row is read again.Then again 2nd row.

This will decrease the amount of memory you need and you may not need extra DDR memory.I hope I didnt confuse you much.

--vipin
https://vhdlguru.blogspot.com/

Thanks you both for your hints, they're valuable

permute, the internal buffer idea sounds just good.

vipinlal I don't think I got it a 100% straight. For what I understood you're saying to use a dual buffering technique to accomplish concurrent reading and writing. To accomplish this I'd need to get 2 standalone DDR RAM chips, wouldn't I ?

I think what vipinlal means is that operate the memory in Ping-Pong behavior, but it do require a good timing control means, you need make sure that the rdclk is faster than the wrclk, and also you need to wirte some status registers to monitor the the operation status. for example, to make sure that the write index is always prior to the read index to prevent data error...