There is no one answer to this, as each application will be different. But I would argue most of your assertions are wrong.
Using library primitives is definitely not the best approach for the smallest option. Unless you are good with placing gates you may restrict optimisations available in the synthesis optimisations. Plus unless you have an optimal solution drawn out, it isn't necessarily optimal. And it will be terrible for any other engineers to pick up.
Also, a deafault in a case statement won't always produce a memory element, it depends on the code. Same with an others choice in vhdl, it is situational.
If else isn't necessarily worse than if else, it can produce the same circuit.
For any language, the best code is one that is well documented and can easily be picked up by another engineer. Id I would always choose this over a highly optimized but difficult to understand design (these designs are usually the least flexible and often get scrapped when changes are needed)
i.e As I know that if else statement produces more circuitry than ternary operator in Verilog. Similarly, default value in Case structure invokes memory elements, and thus produces more circuitry. But these examples are from Verilog.
a = (cond) ? 0 : 1;
if (cond)
a = 0;
else
a = 1;
if (cond == 1'b1)
begin
if (b == 3'b000)
a <= c;
else if (b == 3'b001 && s == 1'b0)
a <= c+1;
else if (b == 3'b001 && s == 1'b1)
a <= c-1;
else if (b == 3'b010)
a <= 0;
else if (b == 3'b011 && s == 1'b0)
a <= c+d;
else if (b == 3'b011 && s == 1'b1)
a <= c-d;
else if (b == 3'b100)
a <= c*d;
end
a <= cond == 1'b1 ? b == 3'b000 ? c :
b == 3'b001 ? s ? c-1 : c+1 :
b == 3'b010 ? 0 :
b == 3'b011 ? s ? c-d : c+d :
b == 3'b100 ? c*d : a : a;
I wanted to create this thread to gather information about the syntax of VHDL that yields the smallest circuitry in synthesis.
(... not true sentences ...)
If you know some of such techniques in VHDL, that produces least circuitry after synthesis then it will be of great value(across different platforms)
(... more not true sentences ...)
Please share your knowledge, any link or document on this topic.
In general every design is different and must be analysed separately in case of generation the smallest circuitry.
I would suggest to focus on functions that the design must do and write your own RTL description tailored for your needs.
Do you need all the functionality that some large "of the shelf" IP Core provide or you need only some part of it? If we talk about the smallest circuitry, then maybe the only way would be to write your own RTL description of that smaller part.
Another factor is to follow vendor recommendations. Find and read appropriate user guides.
Of course the synthesis tool is another factor. You could compare results of the ISE/Vivado, Synplify from Synopsys and Quartus from Altera and pick the smallest circuit for the implementation step.
You need to get the necessary tools for comparison.So, how to compare my design results with Quartus or Synplify, as the target FPGA is also Xilinx FPGA(Zynq 7 series)?
Yes, but when you have a chain of "if-else", they can be different.
For example, the codes below produces the same result, but produces a different circuit:
Code:if (cond == 1'b1) begin if (b == 3'b000) a <= c; else if (b == 3'b001 && s == 1'b0) a <= c+1; else if (b == 3'b001 && s == 1'b1) a <= c-1; else if (b == 3'b010) a <= 0; else if (b == 3'b011 && s == 1'b0) a <= c+d; else if (b == 3'b011 && s == 1'b1) a <= c-d; else if (b == 3'b100) a <= c*d; end
Use ternary op, one possibility is to describe the same is:
Code:a <= cond == 1'b1 ? b == 3'b000 ? c : b == 3'b001 ? s ? c-1 : c+1 : b == 3'b010 ? 0 : b == 3'b011 ? s ? c-d : c+d : b == 3'b100 ? c*d : a : a;
In this case I found that if-else used less logic, but ternary logic produced was way faster.
At first sight, both codes implement the same priority. Also, priority only matters for not fully decoded or non-unique input conditions. In the present case, there are only some undecoded combinations, they either generate a latch (combinational) or keeping the previous registered state, identical in both cases as far as I see.As noted above, these are not the same because of priority.
"Faster" sounds unsubstantiated. Modern synthesis tools generate equal gate level circuits for functionally equivalent HDL code (e.g. ternary versus if else) in most cases. Nobody said that ternary operator is wrong, but tends to make code less readable.Ternary is a very powerful operator, that usually provides a faster circuit, and people usually ignores it simply because they do not like to read it.
Ternary is a very powerful operator, that usually provides a faster circuit, and people usually ignores it simply because they do not like to read it.
For stuff to stick, and others to learn, it has to be clever code that is also understandable by someone with less skill than yourself.
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