[SOLVED] VHDL, which compare function is used?

[std_match]

I found a compare in old code, and I don't understand which function is used.
I can not find ">" for std_logic_vector.
VHDL has a built-in ">" for bit_vector, but it should not be used here?

I have created a small example. Look at line 21.
Tested with Modelsim 6.6d

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Code VHDL - [expand]
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library ieee;
   use ieee.std_logic_1164.all;
   use ieee.numeric_std.all;
 
entity std_logic_vector_compare is
  port(counter_vector_copy : out std_logic_vector(3 downto 0);
    greater_than_6 : out std_logic);
end entity std_logic_vector_compare;
 
architecture test of std_logic_vector_compare is
 
signal counter_vector   : std_logic_vector(3 downto 0);
signal counter : unsigned(3 downto 0) := "0000";
 
begin  -- architecture test
  counter_vector_copy <= counter_vector;
  counter_vector <= std_logic_vector(counter);
 
  process(counter_vector)
  begin
    if counter_vector > "0110" then     -- Which compare function ???
      greater_than_6 <= '1';
    else
      greater_than_6 <= '0';
    end if;
  end process;
 
  stimuli: process
  begin
    wait for 1 us;
    if counter = 15 then
      wait;
    end if;
    counter <= counter + 1;
  end process;
  
end architecture test;

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[TrickyDicky]

hmm, bit of a head scratcher - even works when I only include std_logic_arith, so its not falling out of numeric_std.

- - - Updated - - -

Quartus compiles it without complaining either!
Might be worth posting on comp.lang.vhdl newsgroup

 

[FvM]

even works when I only include std_logic_arith

You mean "even works when I only include std_logic_1164"?

 

[std_match]

It is possible to use the predefined relational operators on all types and arrays of all types,
if the types are the same on both sides of the operator (the array sizes can be different).

The comparison is made element by element, and if one value is left of another in the definition, it is also "less than".

For std_logic_vector, this means that 'X' is less than '0' and 'Z' is greater than '1'.

 

[FvM]

It is possible to use the predefined relational operators on all types and arrays of all types

That's also my assumption. Specific functions and operators for std_logic_vector are required by the different result type.