Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

VHDL - What am I doing wrong?

Status
Not open for further replies.

jelydonut

Full Member level 4
Joined
Dec 27, 2002
Messages
239
Helped
3
Reputation
6
Reaction score
0
Trophy points
1,296
Activity points
1,730
vhdl to_integer

Im trying to make a 32x8 memory, but can only write, cannot read. I need the data bus to be bidirectional as well..

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;

entity memories is
port(
address : in std_logic_vector(4 downto 0);
read : in std_logic;
write : in std_logic;
data : inout std_logic_vector(7 downto 0);
);
end memories;

architecture memories of memories is
type Memory_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal Addr : Memory_Image(0 to 31);
begin
process (read, write)
begin
if (read = '1') then
data <= Addr(to_integer(unsigned(address)));
end if;
if (write = '1') then
Addr(to_integer(unsigned(address))) <= data;
end if;
end process;
end memories;
 

irum4

Member level 3
Joined
Nov 5, 2001
Messages
56
Helped
5
Reputation
10
Reaction score
3
Trophy points
1,288
Activity points
294
to_integer vhdl

You must specify data output value

if (read = '1') then
data <= Addr(to_integer(unsigned(address)));
else-- :!:
data <= (others =>'Z');--:!:
end if;
 

vomit

Full Member level 2
Joined
Jun 14, 2002
Messages
148
Helped
14
Reputation
28
Reaction score
4
Trophy points
1,298
Activity points
1,527
to_integer vhdl library

jelydonut said:
Im trying to make a 32x8 memory, but can only write, cannot read. I need the data bus to be bidirectional as well..
architecture memories of memories is
type Memory_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal Addr : Memory_Image(0 to 31);
begin
process (read, write)
begin
if (read = '1') then
data <= Addr(to_integer(unsigned(address)));
end if;
if (write = '1') then
Addr(to_integer(unsigned(address))) <= data;
end if;
end process;
end memories;
Also you need to add address to the sensitivity list of the process so you read the new address when it changes while read stays '1'.

There's also no x handling. If to_x01(write)='X' the current address could be invalidated so you should dump "XXX..XX" into that memory location.
If the address is invalid while writing the entire memory should be invalidated.

Finally if you only use 1 process for accessing (r/w) the memory, you can put the memory contents into a variable instead of a signal, that's much more efficient for your simulator (PC memory usage).

If you just want a good SRAM model (like it seems to me) check out
http://tech-www.informatik.uni-hamburg.de/vhdl/models/sram/sram.html
 

Al Farouk

Full Member level 4
Joined
Jan 13, 2003
Messages
191
Helped
16
Reputation
32
Reaction score
16
Trophy points
1,298
Location
Egypt
Activity points
1,854
vhdl using to_integer

Try the following
1- Avoid the inout portdescription and useseparat ports for them. Finally if you want them to share the same data bus use Tri stat buffer enabled by Read and Write separatley.

2-
architecture memories of memories is
type Memory_Image is array (31 downto 0) of std_logic_vector(7 downto 0);
signal Addr : Memory_Image;
begin
process (read, write)
begin
if (read = '1') then
data <= Memory_Image(to_integer(address));
end if;
if (write = '1') then
Memory_Image(to_integer(address)) <= data;
end if;
end process;
end memories;
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top