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VHDL warning: Xst:647 - Input is never used.

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WR

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Hi every one,
I got this warning:

WARNING:Xst:647 - Input <sel2> is never used.
Unit <nestedif_warning> synthesized.

when Synthesizing the following code:

process(sel1, sel2)
begin
if sel1 = '1' then
f<='0';
if sel2 = '1' then
z<='0';
end if;
else
f<='1';
end if;
end process;


Thanks,
 

Thiago

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Re: VHDL warning help

Hello WR,


The signal z is always 0, that's why the synthesizer ignore the input sel2. You have to assign the signal z inside this process. [/b]
 

Iouri

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VHDL warning help

process(sel1, sel2)
variable temp: std_logic_vector(1 downto 0)
begin
temp := sel1 & sel2;
case(temp)
when "10" | "11" =>
f <= '0';
when "01" =>
z <= '1';
when others =>
f <= '1';
end case
end process;


if this for FPGA/CPLD you migt need to include clock
to avoid latches

regards,
 

WR

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Re: VHDL warning help

Hi,
I new that I can do it by case statement ... but what is wrong with that code by if statement..even if there is a clock or if z<='1' .. it will give the warning.
 

tkbits

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Re: VHDL warning help

Thiago said:
The signal z is always 0, that's why the synthesizer ignore the input sel2. You have to assign the signal z inside this process. [/b]
In other words, you need to specify what other values z can have, and what conditions produce those other values.

If you don't, sel2 is redundant and the optimizer can (and did) remove it.
 

vlsi_whiz

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Re: VHDL warning help

You have to mention all values of 'f' and 'z' in the code.. and also you haven't checked for sel2 in the first condition and sel1 in the 2nd.

if (sel1 = '1' AND sel2 = '0')
...
....
if (sel2 = '1' AND sel1 = '0')

If you dont explicitly mention this...then the loops can get executed when both sel1 and sel2 are '1'. So the synthesis tool will remove the second loop as it is redundant. In other words you have to check the other signals also in your IF loop.
 

salma ali bakr

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Re: VHDL warning help

u should either mention F and Z in each branch of your "if" statement
or have initial values for both of them and mention just the changed ones in the "if" statement branches
 

WR

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VHDL warning help

Thanks.
 

Tan

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Re: VHDL warning help

Does WARNINGS really matter in the synthesis process.

what happens if they are ignored..?
Should we really consider and debug WARNINGS for effective programming. ?

Please explain.
 

WR

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VHDL warning help

Hi Tan,

Yes, the output 'z' in my case will not change by changing the input (x1).

This means that you design will not work properly.

Regards.
 

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