VHDL? Verilog? Verilog-A? Verilog-AMS?

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Beardolphinaries

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Hi, could anyone tell what's the difference among
VHDL, Verilog, Verilog-A and Verilog-AMS please?
Thanks a lot.
 

Dear Beardolphinaries :

I think:
VHDL / Verilog: for digital design and mixed mode simulate
verilog-A : for analog designer, not good idea for mixed mode mode simulate


mpig
 

Hello,

VHDL and Verilog are competitors and both are for digital design.
With Verilog-A you can program in your analog design some ideal digital cells.
Verilog-AMS is for mixed simulations.

olzanin
 

I use verilog for purely digital stuff.
VHDL is used mainly in Europe and Japan.
Not much in the US. Verilog-A to model analog stuff
when I need speedy sim time. Have not used Verilog-AMS yet but I think Verilog A is a subset of AMS.
 

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