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I wish not to divulge into which language is easiier / better / faster etc.
I have used all the 3 languages and I can summarise as
VHDL : this is a hardware descriptive language , was one of the eariliest follows highly descriptive languge and very strictly adrehers to hardware description . Harder to code but once you get the code compliling you genrally don't see much of a synthesis / simulation mismatch. Major disadvantage most synthesis tools don't give out vhdl netlist , if you intend to do netlist validation/simulation.
verilog : syntax is similar to that of 'c' programming language hence most people find it easier to code in this language. But BAD CODING STYLE can cause race condition/ and simulation and synthesis mismatches. But great advantage is that doing post synthesis net list valdiaion is not much of an effort since you can obtain a veilog netlist from your synthesis tool
SystemC : All along verilog / vhdl was the language that was used to verify the design . But with time the designs started getting complex and need was felt to verify at a higher level of abstraction this is where the HVL ( hardware verification languages) came into picture. SystemC is based on c++ infact it is only a c++ library that can be used to model hardware. Major disadvantage of this that there is not a lot of support if you want for synthesis in systemc by any vendor and so it is still majorlly used only for verifiacation.
And my experice with these languages is that they are difficult onlly to begin with but not so tough that you should not put effort into them. I hope this thread does not end up with a discussion on what is superior .