Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

VHDL/Verilog Guidance - Cache

Status
Not open for further replies.

dchan

Newbie level 3
Joined
Aug 22, 2010
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,303
Hi All,
I am a beginner to VHDL/Verilog coding and am trying to implement a feasible project.
I am considering 2 ideas:
1) Implementation of a Fully Associative or Set Associative Cache
2) Cache coherence in a 2-processor system

If you could please guide me on Verilog or VHDL coding references and which one of the above 2 would be a better topic to implement both from the learning and feasibility perspective it would be very helpful.

Thank you.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top