FvM said:Of course, you can use ieee.numeric_std instead of ieee.std_logic_arith. But as a fact, most vendor packages are still based on std_logic_arith. I prefer it, too. The above conversions are also from std_logic_arith.
integer to std_logic_vector conversion needs to clarify the intended numeric representation first, so you can either use TO_SIGNED() or TO_UNSIGNED() first, casting the result to STD_LOGIC_VECTOR:
slvsignal <= STD_LOGIC_VECTOR(TO_UNSIGNED(intval,bitlen));
vomit said:Personally I only use std_logic_vectors for
- groups of std_logics that are not a number, e.g. bitmasks, status bits, ...
- top-level I/O buses because synthesis tools have a tendency to write out netlists with "std_logic_vector" for buses, even if the original VHDL code specifies "signed" or "unsigned". This way, the synthesised netlist still plugs into the testbench without having to write wrappers.
package myentitypack is subtype t_AddressBus is unsigned(9 downto 0); subtype t_DataBus is std_logic_vector(7 downto 0); component myentity is ... port ( Address : t_AddressBus; Data : t_DataBus; ... ); end component myentity; end package myentitypack;