VHDL vector array question

Status
Not open for further replies.

bubuta77

Member level 4
Joined
Jul 6, 2008
Messages
78
Helped
19
Reputation
38
Reaction score
18
Trophy points
1,288
Location
Israel
Activity points
1,749
i use following vector array:
type arr1 is array(0 to 2) of STD_LOGIC_VECTOR(11 downto 0);
constant data:arr1:=("000000000100","000000111111","111111000000");

if i want to access bit 2 at vector data(0) it will be correct to write:
temp<=data(0,2); -- it will be 1?
 

no. That addressing is if you had a 2D array. You have a 1D array of 1D arrays, so the correct way to access it would be:

temp <= data(0)(2);
 
Status
Not open for further replies.

Similar threads

Cookies are required to use this site. You must accept them to continue using the site. Learn more…