you have several problems here:
The first is not really a problem, its more of a gripe. Why are you using a std_logic_vector? its not a number, and treating it as a number means you have to include the non-standard std_logic_unsigned/signed package which means you can never do signed and unsigned things in the same file. The IEEE standard package to do this is numeric_std that defines signed and unsigned types.
Secondly, you do not have a "variable" length memory - it is fixed at compile time (defaulting to 8). The problem is you have a 16 bit address bus that converts to 0 to 2^16-1, way more than you have spaces in the memory. When you put in an address higher than 7, you will get an error when simulating because of the out of range error. Why not declare address as an integer instead? you know you're allowed types other than std_logic_vectors on ports right?
Code:
entity arb_mem_bank is
port (
...
address : integer range 0 to length_of_reg;
);
end entity arb_mem_bank;
Next error - you cannot reset a memory, in either Xilinx or Altera, so unless you want this to synthesize to registers (and take a long time and a lot of resources as the memory gets bigger) remove the synchronous reset on the memory. There is usually no need to reset a memory as contents just get over-written.
Next point - you only need clk in the sensitivity list of the process.
next - do not output the entire memory. The contents should only be visible via the read address, not the entire lot. This is probably causing the compiler problems.
So overall - you have several problems. Creating infered memories in FPGAs is very simple in VHDL, as long as you follow the following template (some things may be slightly altered, depending on your FPGA target - but please read their coding guidelines)
Code:
entity my_mem is
generic (
MEM_BITS : natural;
D_WIDTH : natural
);
port (
clk : in std_logic;
rd_addr : in integer range 0 to 2**MEM_BITS-1;
rd_en : in std_logic;
rd_data : out std_logic_vector(D_WIDTH-1 downto 0);
wr_addr : in integer range 0 to 2**MEM_BITS-1;
wr_en : in std_logic;
wr_data : in std_logic_vector(D_WIDTH-1 downto 0)
);
end entity my_mem;
architecture rtl of my_mem is
type mem_array_t is array(0 to 2**MEM_BITS-1) of std_logic_vector(D_WIDTH-1 downto 0);
signal mem : mem_array_t;
begin
process(clk)
begin
if rising_edge(clk) then
if wr_en = '1' then
mem(wr_addr) <= wr_data;
end if;
------------------------------------------------------------------------
--Altera may require you to register the rd_addr before reading
------------------------------------------------------------------------
if rd_en = '1' then
rd_data <= mem(rd_addr);
end if;
end if;
end process;
end architecture rtl;