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VHDL unsigned to signed conversion.

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zoulzubazz

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hey guys,

i am getting data from a 12 bit ADC into an FPGA, so '000000000000' represents the lowest ADC value and '111111111111' represents the highest value ADC(unsigned). Now to manipulate this data inside an FPGA I am having to cast the ADC input into a 'signed' value like so,

adc_sgn := signed(adc_unsgn);

My question is wouldn't this conversion from unsigned to signed change the value and 12 bit ADC word holds, since (for example) '1111' in unsigned representation is 15 where as it is -6 in signed 2's compliment representation? Thanks.
 

std_match

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If you want to keep it at 12 bits, you should invert the highest bit to get a correct sign bit. This means that the midrange value of the ADC will be represented as zero. If you want to keep the ADC value zero as zero, you must go to 13 bits and set the highest bit to '0'.
 

zoulzubazz

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I want to retain the 12 bits, but I cant get my head around 'the midrange value of the ADC will be represented as zero' could you kindly provide an example. thanks.
 

TrickyDicky

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ADCs often use offset binary for their "signed" values. So x"800" is actually 0v. in VHDL, you need to do the following to treat it as signed:

a <= ip - OFFSET;
b <= signed(a);

btw. "1111" in signed is actually -1, not -6. "1000" = -7
 

std_match

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a <= ip - OFFSET;
b <= signed(a);

btw. "1111" in signed is actually -1, not -6. "1000" = -7

If OFFSET is the midrange value (only the highest bit set), the subtraction is identical to inverting the highest bit of "a". I don't know if all synthesis tools understand that.

"1000" as signed is -8
 
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