VHDL unconstrained arrays

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shaiko

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In VHDL you can do the following assignment :

Code: 
x <= ( others => '1' ) ;
However,
You cannot compare this way :
Code: 
if x = ( others => '1' ) then
Is there a way to do it compactly without writing the whole long vector?
Code: 
if x =  "1111111111111111111111111111111111111111" then
 

Good question, I will like to know that too!

But for me, since "1111111111111111111..." is a constant, will consider to declare CONSTANT in generic or library package named CONSTANT32bit1

then

Code: 
if x = CONSTANT32bit1 then
..
..
end if;

if y = CONSTANT32bit1 then
..
..
end if;

---etc
 

either declare a handy constant:

constant ONES : std_logic_vector(x'range) := (others => '1');

if x = ONES then

or create the vector properly:

if x = (x'range => (others => '1') ) then

I think the first one is better.
 
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    shaiko

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IIRC, you can do "x = (x'range => '1')" or "signed(x) = -1"
 

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