VHDL UART doesn't work

[nathand]

Hi, i'm trying to develop an UART on a Nexys2 board, and I'm desperated.

Here's the piece of code of the receiver. The simulation is ok but then in the board doesn't work with Hyperterminal.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity UART_receiver is
	port(
		CLK, RST : in STD_LOGIC;
		Rx : in STD_LOGIC;
		s_tick : in STD_LOGIC;
		rx_done_tick : out STD_LOGIC;
		intData : out STD_LOGIC_VECTOR(7 downto 0);
		contando : out STD_LOGIC
	);

end UART_receiver;

architecture Behavioral of UART_receiver is

	subtype miInteger is integer range 0 to 20;
	type state_type is (idle, start, data, stop);
	signal state_reg : state_type;
	signal clockCounter : miInteger;
	signal bitCounter : miInteger;
	
	begin
		process(CLK, RST)
			begin
				if(RST = '1') then
					clockCounter <= 0;
					state_reg <= idle;
					intData <= (others => '0');
				elsif(CLK'EVENT AND CLK = '1') then
				
					case state_reg is
						when idle =>
							if(Rx = '0') then	
								clockCounter <= 0;
								state_reg <= start;
							end if;
						
						when start =>
							if(clockCounter >= 7) then
								clockCounter <= 0;
								bitCounter <= 7;
								state_reg <= data;
							else
								clockCounter <= clockCounter + 1;
							end if;
							
						when data =>
							if(clockCounter >= 15) then
								clockCounter <= 0;
								intData(7 - bitCounter) <= Rx;
								if(bitCounter = 0) then
									state_reg <= stop;
									bitCounter <= 7;
								else
									bitCounter <= bitCounter - 1;
								end if;
							else
								clockCounter <= clockCounter + 1;
							end if;
							
						when stop =>
							if(clockCounter >= 15) then
								state_reg <= idle;
							else
								clockCounter <= clockCounter + 1;
							end if;
					end case;
				end if;
			end process;

end Behavioral;

I've been more than a month working with this with no result... Every help is thanked.

 

[FvM]

Code is still incomplete, e.g. tx_done missing. Are you sure about baudrate and clock frequency?

Chipscope can answer why the UART isn't working correctly.

Usually asynchronous inputs like RX are synchronized to the design clock by a double register before processing it in the synchronous logic.

As a minor correction, waiting a full bit duration in stop state can result in problems receiving a continuous stream with positive baud rate deviation.