VHDL UART code problem for xilinx spartan-6 sp605

[shedo]

Hi all,
I need to implement an uart module written in vhdl to comunicate with another module, I have tried to use this **broken link removed** (source) with this main:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity MESSAGE_GEN is
  port (  -- General
          CLOCK_Y3            :   in      std_logic;
          USER_RESET          :   in      std_logic;
			 SEND 						: in STD_LOGIC;	
          -- UART
          USB_RS232_RXD       :   in      std_logic;
          USB_RS232_TXD       :   out     std_logic
       );
end MESSAGE_GEN;

architecture RTL of MESSAGE_GEN is
  -- Functions
  --Type definition
  type hello_world_type is array (0 to 4) of integer range 0 to 255;
	
  --Hello world type definition
  signal hello_world : hello_world_type := (10,101,108,108,79);
  signal state : integer range 0 to 299;
  -- Component Declarations
  component UART is
    generic 
    (
      BAUD_RATE             : positive;
      CLOCK_FREQUENCY       : positive;
      TX_FIFO_DEPTH         : positive;
      RX_FIFO_DEPTH         : positive
    );
    port 
    (  -- General
      CLOCK                 :   in      std_logic;
      RESET                 :   in      std_logic;    
      TX_FIFO_DATA_IN       :   in      std_logic_vector(7 downto 0);
      TX_FIFO_DATA_IN_STB   :   in      std_logic;
      TX_FIFO_DATA_IN_ACK   :   out     std_logic;
      RX_FIFO_DATA_OUT      :   out     std_logic_vector(7 downto 0);
      RX_FIFO_DATA_OUT_STB  :   out     std_logic;
      RX_FIFO_DATA_OUT_ACK  :   in      std_logic;
      RX                    :   in      std_logic;
      TX                    :   out     std_logic
    );
  end component UART;
    
  signal CLOCK                          : std_logic := '0';
  signal send1								    : std_logic;

  signal reset_d0, reset                : std_logic := '0';
  signal uart_rxd_d0                    : std_logic := '0';
  signal uart_rxd                       : std_logic := '0';
  signal uart_txd_d0                    : std_logic := '0';
  signal uart_txd                       : std_logic := '0';
          
  signal uart_tx_fifo_data_in           : std_logic_vector (7 downto 0) := (others => '0');
  signal uart_tx_fifo_data_in_stb       : std_logic := '0';
  signal uart_tx_fifo_data_in_ack       : std_logic := '0';
  signal uart_rx_fifo_data_in           : std_logic_vector (7 downto 0) := (others => '0');
  signal uart_rx_fifo_data_in_stb       : std_logic := '0';
  signal uart_rx_fifo_data_in_ack       : std_logic := '0';


  -- Messages
  constant MSG_CONFIGURED               : string := "FPGA con";

begin

  CLOCK       <= CLOCK_Y3;

  DEGLITCHER : process (CLOCK)
  begin
      if rising_edge(CLOCK) then
          reset_d0        <= USER_RESET;
          reset           <= reset_d0;
          uart_rxd_d0     <= USB_RS232_RXD;
          uart_rxd        <= uart_rxd_d0;
          uart_txd_d0     <= uart_txd;
          USB_RS232_TXD   <= uart_txd_d0;
      end if;
  end process DEGLITCHER;
  
  UART_inst1 : UART
  generic map 
  (
    BAUD_RATE               => 115200,
    CLOCK_FREQUENCY         => 100000000,
    TX_FIFO_DEPTH           => 1023,
    RX_FIFO_DEPTH           => 1023
  )
  port map 
  (
    CLOCK                   => CLOCK,
    RESET                   => reset,   
    TX_FIFO_DATA_IN         => uart_tx_fifo_data_in,
    TX_FIFO_DATA_IN_STB     => uart_tx_fifo_data_in_stb,
    TX_FIFO_DATA_IN_ACK     => uart_tx_fifo_data_in_ack,
    RX_FIFO_DATA_OUT        => open,
    RX_FIFO_DATA_OUT_STB    => open,
    RX_FIFO_DATA_OUT_ACK    => '0',
    RX                      => uart_rxd,
    TX                      => uart_txd
  );

  
  MESSAGE_SENDER : process (CLOCK)
  begin
    if rising_edge(CLOCK) then
      if reset = '1' then
        uart_tx_fifo_data_in              <= (others => '0');
        uart_tx_fifo_data_in_stb          <= '0';
		  state										<= 0;
      else
        if uart_tx_fifo_data_in_ack = '1' then
          uart_tx_fifo_data_in_stb        <= '0';
        end if;
		  if (send='1' and send1='0') then
				if uart_tx_fifo_data_in_stb = '0' then
					-- Send new line character and go to next state.
					uart_tx_fifo_data_in_stb  <= '1';
					uart_tx_fifo_data_in      <= std_logic_vector(to_unsigned(hello_world(state),8));
					state <= state+1;
				end if;
		  end if;
		  send1 <= send;
      end if;
    end if;
  end process MESSAGE_SENDER;
end RTL;

with this ucf constrain file:

NET "CLOCK_Y3" LOC = AB13;
NET "CLOCK_Y3" TNM_NET = "CLOCK_Y3";
TIMESPEC TS_CLOCK_Y3 = PERIOD "CLOCK_Y3" 100000 KHz;

NET "USER_RESET" LOC = C1;
NET "SEND" LOC = F3;

## 24 on U4
NET "USB_RS232_RXD" LOC = H17;
## 25 on U4
NET "USB_RS232_TXD" LOC = B21;

But the result is:

ÀøÀøÀøÀøÀøÀøÀøÀøÀøÀøÀøÀøÀøÀøÀøÀ

I use tera term with: Baud rate: 115200, 8 bit data,parity none,1 stop bit and flow control: none

I have spartan-6 sp605 and i use xilinx design suite 13.3



Please can you help me?



Thanks Ivan

 

[shedo]

if you can not help me with this code can you advise an uart model in vhdl for the xilinx SP605?

 

[TrickyDicky]

Have a look on opencores.org.

 

[shedo]

Hi Pete,

I found that the problem is the clock. I use AB13 pin and I have seen at page 28 of "Hardware user guide" that this one is a X2 27MHz OSC so I set in the code: CLOCK_FREQUENCYositive := 27000000; and now it'is working!!!
I don't know how to use the U6 200MHZ OSC in order to set 100Mhz... if you have some suggestions you are welcome...

Thanks a lot for your help!!!