VHDL Type Conversion : from SIGNED to STD_LOGIC_VECTOR

Status
Not open for further replies.

omara007

Advanced Member level 4
Joined
Jan 6, 2003
Messages
1,237
Helped
50
Reputation
102
Reaction score
16
Trophy points
1,318
Location
Cairo/Egypt
Activity points
9,716
vhdl type conversion

Hi Guys ..

I want to convert between the 2 vector types (SIGNED to STD_LOGIC_VECTOR). I used the function 'CONV_SIGNED (ARG:SIGNED, SIZE:INTEGER) return STD_LOGIC_VECTOR;' but it always gives me ZEROs in the returned STD_LOGIC_VECTOR regardless of the value contained in the SIGNED vector!! ..

So, how can I convert between these 2 types ?
 

vhdl signed

Please try This Function

***convert signed to std_logic_vector***

<slv_sig> = CONV_STD_LOGIC_VECTOR(<signed_sig>, <integer>)


***convert std_logic_vector to signed****
<signed_sig> = CONV_SIGNED(<sul_sig>, <integer>)
 
std_logic_vector to signed

BuBEE said:
Please try This Function

***convert signed to std_logic_vector***

<slv_sig> = CONV_STD_LOGIC_VECTOR(<signed_sig>, <integer>)


***convert std_logic_vector to signed****
<signed_sig> = CONV_SIGNED(<sul_sig>, <integer>)
Click to expand...

i tried it .. outside the clocked process .. in a normal combinational statement , and it gave me strange behavior .. some signals inside the resultant vector are 'X' .. and some others are '0' .. don't know why !!
 

vhdl signed to std_logic_vector

Try it !!!

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;

ENTITY test IS
PORT(
a : OUT signed (7 downto 0);
b : IN std_logic_vector (7 downto 0)
);
END test ;

ARCHITECTURE struct OF test IS
begin


label1: for i in 0 to a'LENGTH-1 generate
a(i) <= b(i);
end generate label1;
END struct;
 

type conversion in vhdl


This is from STD_LOGIC_VECTOR to SIGNED .. but anyhow I will try to change it from SIGNED to STD_LOGIC_VECTOR ..
 

vhdl unsigned to std_logic_vector

No problem )

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;

ENTITY test1 IS
PORT(
a : IN signed (7 downto 0);
b : OUT std_logic_vector (7 downto 0)
);
END test1;

ARCHITECTURE struct OF test1 IS
begin

label1: for i in 0 to b'LENGTH-1 generate
b(i) <= a(i);
end generate label1;
END struct;

as by definition:
type SIGNED is array ... of std_logic
type STD_LOGIC_VECTOR is array ... of std_logic
!!!!!! ))

Best regards.
 

vhdl conv

Are there any good tricks to convert between std_logic_vector and signed/unsigned?

I am reading textbook by peter j. adhenden, but there seems to be a distinct divide between std_logic_vector and IEEE math libraries.. One can not simply convert back and forth without a troublesome custom function.
 

unsigned to std_logic_vector


Read FAQ at www.vhdl.org/comp.lang.vhdl

Ajeetha, CVC
www.noveldv.com
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…