VHDL tristate buffers

[shaiko]

The simplest way I know to describe a tristate buffer is :

io_port <= driver when direction = '1' else 'Z'

But what if I do it in a more complex way - In a registered output FSM for example ?

--------------------------------
if rising_edge (clk) then

case state is

when state_1 =>
io_port <= ( others => 'Z' ) ;
registered_io_port <= io_port ;

when state_2 =>
io_port <= driver ;
--------------------------------


Will the above FSM code inffer (with guaranteed certainty) a tri-state buffer for "io_port" ?

 

[std_match]

The basic principle should work, but your code has a potential problem. The code for state_1 will tristate io_port from the current rising_edge, but the registered_io_port will store the value before the current rising_edge. The value you read is valid one clock cycle after you set the output to 'Z'.

 

[shaiko]

Sure,
But that's the case with any reistered signal.
Output is good only at the next edge.

 

[TrickyDicky]

that wont work, you cannot register a 'z' value. you can however register the enable value that tristates the output.

 

[shaiko]

that wont work, you cannot register a 'z' value.

I'm not trying to register the 'Z' value - I want to register the logic level at the "inout" pin when it's tristated...

 

[std_match]

that wont work, you cannot register a 'z' value. you can however register the enable value that tristates the output.

What you say is that the 'Z' assignment can't be done in a clocked process?

I see nothing wrong if we just see it as VHDL code, but I can understand if synthesis tools can't handle it.

 

[dave9000]

Precision Synthesis has got no problem with it. I have a working design like this:

In the FSM process:
   when s2 => my_bus_cld <= data_out;
   when s4 => my_bus_cld <= (others => 'Z');
   when s5 => data_in <= my_bus;     -- NOTE: not my_bus_cld

Outside the process:
   my_bus <= my_bus_cld;

my_bus is the inout port. Note that I wait a clock tic before samplig the data.

 

[shaiko]

std_match, you say:
"but I can understand if synthesis tools can't handle it" - I don't.
What's wrong with sampling in the logic level of an inout port ?
Can you suggest another way ?

 

[std_match]

std_match, you say:
"but I can understand if synthesis tools can't handle it" - I don't.
What's wrong with sampling in the logic level of an inout port ?
Can you suggest another way ?

The last posts have not been discussing the reading of the port. We are discussing the tristating by setting the port to 'Z' in a clocked process. It isn't a problem for the VHDL language, but a synthesis tool must create at least one extra register for each group of outputs that are tristated together. The special value 'Z' can not be held in the same register as the "normal" value.

 

[FvM]

What's wrong with sampling in the logic level of an inout port ?

Nothing is wrong, it's just misunderstanding, I presume. You didn't say clearly that io_port is an external pin and registered_io_port an internal signal sampled from this port. I also didn't understand it at first sight.