This question is flawed.
VHDL will let you create a bus of any width.
However certain FPGA's might limit the width because downstream there is a hard mac primitive that uses a certain dimension. The place and route (par) tools are clever and my utilise two 18bit width fifos to create a 32 bit fifo ...for example.
at #3 I've shifted more in one clock cycle before.
Edit -------------
type BIT_VECTOR is array (NATURAL range <>) of BIT;
Therefore I suppose if we wanted to be picky, we could say the range 2^x of the compiler is the databus limit. This is more a limit imposed on the fact computers are x (32, 64 etc) bits capable rather than the concept that the bus and language could be infinite.