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VHDL testbench SDF file annotation problem

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joe82

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which file to annotate sdf

Hello,
I'm trying to annotate an SDF file to a simple VHDL testbench file i've wrriten.
My synthesized Desing is a simple MUX2 i've found on the net. I have synthesized the file and created an SDF file using Design Vision.

When trying to elaborate the testbench file and using the sdf annotate option (i'm using NClaunch) i get the following errors:

ncelab -snapshot worklib.mux2:syn_verilog -work worklib -cdslib /hm/cds.lib -logfile ncelab.log -errormax 15 -access +wc -status -sdf_cmd_file sdf.cmd worklib.mux2_tb
ncelab: 08.10-s006: (c) Copyright 1995-2008 Cadence Design Systems, Inc.
ncelab: *W,ARCMRA: Elaborating the WORKLIB.MUX2_TB:MUX2_TB_ARCH, MRA (most recently analyzed) architecture.
ncelab: *W,SDFCTE: Module MUX2_TB of instance : doesn't match SDF celltype of MUX2, skipping annotation <./mux2.sdf, line 15>.
ncelab: *W,SDFINF: Instance G2 not found at scope level <top-level> <./mux2.sdf, line 22>.
ncelab: *W,SDFINF: Instance G3 not found at scope level <top-level> <./mux2.sdf, line 18>.
ncelab: *W,SDFANS: Attempt to annotate to non-existent source port A at scope level <./mux2.sdf, line 19>.
ncelab: *W,SDFINF: Instance G1 not found at scope level <top-level> <./mux2.sdf, line 23>.
ncelab: *W,SDFANS: Attempt to annotate to non-existent source port B at scope level <./mux2.sdf, line 21>.
ncelab: *W,SDFANS: Attempt to annotate to non-existent source port SEL at scope level <./mux2.sdf, line 23>.
ncelab: *W,SDFINF: Instance G3 not found at scope level <top-level> <./mux2.sdf, line 29>.
ncelab: *W,SDFINF: Instance G2 not found at scope level <top-level> <./mux2.sdf, line 38>.
ncelab: *W,SDFINF: Instance G1 not found at scope level <top-level> <./mux2.sdf, line 50>.
ncelab: Memory Usage - 17.7M program + 15.1M data = 32.8M total
ncelab: CPU Usage - 0.0s system + 0.0s user = 0.1s total (0.3s, 23.4% cpu)
ncelab: ANNOTATION Time - 0.0s
Click to expand...

some information that might help:
The sdf cell name is MUX2
the Testbench architecture name is MUX2_TB_ARCH

I have tried using the scope option and wrote everything i can think about yet still i get this or similar errors.
Btw- Elaborating the MUX2 design (not the mux2_tb) with the sdf file i do not get the errors for obious reasons, But then i can not run the testbench on the elaborated snapshot, or can i?

Many Thanks,
Joe.
 
Last edited by a moderator:

OK i'll try to simplify my question:

I have 3 files: MUX2 architecture file, MUX2_TESTBENCH architecture file, sdf file.

I have created an SDF file for the MUX2 design, what is the right way to simulate the design using ncsim?

1. annotate the sdf file to the MUX2 design, elaborate MUX2 design and set the testbench inside ncsim(is it possible to configure a testbench after ncsim is launched?).
2. annotate the sdf file to the MUX2_TESTBENCH design, elaborate MUX2_TESTBENCH and run ncsim with no need to configure the testbench inside ncsim.

Thanks,
Joe.
 

Hi,

I am not familiar with NcSim, but in general you should add the SDF file and set the region (scope) to the part of the design it is for, and start the simulation of your testbench.
In the region you must use the instance labels, e.g.
testbench
dut : toplevel_design
u0 : sublevel
u1 : MUX2
The region should be /testbench/dut/u1 (when the SDF file is for MUX2)

Maybe NcSim does not use forward slashes in the region notation. You can find this in the NcSim documentation.

Devas
 

    J

    joe82

    Points: 2
    Helpful Answer Positive Rating
Oh wow, i've been trying to run it with many different combinations of entity/component in the scope field instead of using the architecture/port map (of the testbench). Your post helped me try it the right way and it works now. Thanks!
 

joe82 said:
Oh wow, i've been trying to run it with many different combinations of entity/component in the scope field instead of using the architecture/port map (of the testbench). Your post helped me try it the right way and it works now. Thanks!
Click to expand...

Can you explain in details about how to resolve this problem? I do not understand what you mean actually. Thank you.8-O
 

Please upload your design files and sdf. I will take a look and see whether I can help or not.
 

Thank you very much for your reply.
My design has two modules: sender and receiver. So I have two top module for these two modules (sender.v and receiver.v).
Firstly, I use a top module (top.v) to contain these two modules. Just like;
Code VHDL - [expand]
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/////top.v/////
module top(
            // Inputs
            rst, 
            i0, i1, i2, i3, oa,
            // Outputs
            o0, o1, o2, o3, ia,
            checkout0, checkout1, checkout2, checkout3
            );
   
.....
sender sender(...);
receiver receiver(....);
 
endmodule


I use a testbench (test_top.v) of the top module to do simulation. I use Design compiler to synthesize the top module and get the gate-level netlist (top.v) and the sdf file (top.sdf). I put the system task $sdf_annotate("../data/top.sdf",r) in the testbench. Then I use the script below to do frontend simulation.
...
Code: 
ncvlog  ../data/top.v
ncvlog -sv ../test_top.v
ncelab -timescale 1ns/1ps -access +rwc worklib.test_top
ncsim -tcl test_top

Then no errors or warnings occur. So this should be a right flow.

But I need to add some behavioral level module between sender and receiver which should not be synthesized. So I need to synthesize the two modules respectively.
I get two gate-level netlists (sender.v and receiver.v) and two sdf files (sender.sdf and receiver.sdf). Then I wrote a testbench to include these two modules and put the tasks $sdf_annotate("../data/sender.sdf",s); $sdf_annotate("../data/receiver.sdf",r); in the initial module of the testbench.
Then I ran this script to simulate the whole design.
...
Code: 
ncvlog  ../data/ultra_sender.v
ncvlog  ../data/ultra_receiver.v
ncvlog -sv ../test_top.v
ncelab -timescale 1ns/1ps -access +rwc worklib.test_top
ncsim -tcl test_top
...

Then, errors occur when it read the sender.sdf (I am confused of why receiver.sdf can be correctly read while the sender.sdf can not, actually I use the same dc script to synthesize these two modules with only a bit constrains. The sender module is very simple)
Errors are:

.................................
Reading SDF file from location "../data/sender.sdf"
Reading SDF file from location "../data/receiver.sdf"
ncelab: *W,SDFANS: Attempt to annotate to non-existent source port OB at scope level CheckGen_6__wrapperPE.co2.U2 <../data/sender.sdf, line 647>.
ncelab: *W,SDFAND: Attempted INTERCONNECT annotation to non-existent destination port A at scope level CheckGen_6__wrapperPE.co2.U2 <../data/sender.sdf, line 653>.
ncelab: *W,SDFAND: Attempted INTERCONNECT annotation to non-existent destination port B at scope level CheckGen_6__wrapperPE.co2.U2 <../data/sender.sdf, line 654>.
ncelab: *W,SDFAND: Attempted INTERCONNECT annotation to non-existent destination port S at scope level CheckGen_6__wrapperPE.co2.U2 <../data/sender.sdf, line 655>.
ncelab: *W,SDFAND: Attempted INTERCONNECT annotation to non-existent destination port I at scope level CheckGen_6__wrapperPE.co2.U3 <../data/sender.sdf, line 652>.
ncelab: *W,SDFCTE: Module BUFEHD of instance test_top.s.CheckGen_7__wrapperPE.co2.U4 does not match SDF celltype of INVCHD, skipping annotation <../data/sender.sdf, line 6480>.
ncelab: *W,SDFCTE: Module BUFEHD of instance test_top.s.CheckGen_7__wrapperPE.co1.U4 does not match SDF celltype of INVCHD, skipping annotation <../data/sender.sdf, line 6532>.
ncelab: *W,SDFCTE: Module BUFEHD of instance test_top.s.CheckGen_6__wrapperPE.co2.U4 does not match SDF celltype of INVCHD, skipping annotation <../data/sender.sdf, line 6893>.
ncelab: *W,SDFCTE: Module MUX2EHD of instance test_top.s.CheckGen_6__wrapperPE.co2.U3 does not match SDF celltype of INVCHD, skipping annotation <../data/sender.sdf, line 6902>.
ncelab: *W,SDFCTE: Module INVCHD of instance test_top.s.CheckGen_6__wrapperPE.co2.U2 does not match SDF celltype of MXL2CHD, skipping annotation <../data/sender.sdf, line 6911>.
ncelab: *W,SDFCTE: Module BUFEHD of instance test_top.s.CheckGen_6__wrapperPE.co1.U4 does not match SDF celltype of INVCHD, skipping annotation <../data/sender.sdf, line 6945>.
ncelab: *W,SDFCTE: Module BUFEHD of instance test_top.s.CheckGen_5__wrapperPE.co2.U4 does not match SDF celltype of INVCHD, skipping annotation <../data/sender.sdf, line 7306>.
ncelab: *W,SDFCTE: Module BUFEHD of instance test_top.s.CheckGen_5__wrapperPE.co1.U4 does not match SDF celltype of INVCHD, skipping annotation <../data/sender.sdf, line 7358>.
ncelab: *W,SDFCTE: Module BUFEHD of instance test_top.s.CheckGen_4__wrapperPE.co2.U4 does not match SDF celltype of INVCHD, skipping annotation <../data/sender.sdf, line 7719>.
ncelab: *W,SDFCTE: Module BUFEHD of instance test_top.s.CheckGen_4__wrapperPE.co1.U4 does not match SDF celltype of INVCHD, skipping annotation <../data/sender.sdf, line 7771>.
ncelab: *W,SDFCTE: Module BUFEHD of instance test_top.s.CheckGen_3__wrapperPE.co2.U4 does not match SDF celltype of INVCHD, skipping annotation <../data/sender.sdf, line 8132>.
ncelab: *W,SDFCTE: Module BUFEHD of instance test_top.s.CheckGen_3__wrapperPE.co1.U4 does not match SDF celltype of INVCHD, skipping annotation <../data/sender.sdf, line 8184>.
ncelab: *W,SDFCTE: Module BUFEHD of instance test_top.s.CheckGen_2__wrapperPE.co2.U4 does not match SDF celltype of INVCHD, skipping annotation <../data/sender.sdf, line 8545>.
ncelab: *W,SDFCTE: Module BUFEHD of instance test_top.s.CheckGen_2__wrapperPE.co1.U4 does not match SDF celltype of INVCHD, skipping annotation <../data/sender.sdf, line 8597>.
ncelab: *W,SDFCTE: Module BUFEHD of instance test_top.s.CheckGen_1__wrapperPE.co2.U4 does not match SDF celltype of INVCHD, skipping annotation <../data/sender.sdf, line 8958>.
ncelab: *W,SDFCTE: Module BUFEHD of instance test_top.s.CheckGen_1__wrapperPE.co1.U4 does not match SDF celltype of INVCHD, skipping annotation <../data/sender.sdf, line 9010>.
ncelab: *W,SDFCTE: Module BUFEHD of instance test_top.s.CheckGen_0__wrapperPE.co2.U4 does not match SDF celltype of INVCHD, skipping annotation <../data/sender.sdf, line 9371>.
ncelab: *W,SDFCTE: Module BUFEHD of instance test_top.s.CheckGen_0__wrapperPE.co1.U4 does not match SDF celltype of INVCHD, skipping annotation <../data/sender.sdf, line 9423>.
ncelab: *W,SDFCTE: Module AO222HHD of instance test_top.s.SDL_8__dc2_s2.U1 does not match SDF celltype of AO222EHD, skipping annotation <../data/sender.sdf, line 12467>.
ncelab: *W,SDFCTE: Module AO222HHD of instance test_top.s.SDL_6__dc2_s3.U1 does not match SDF celltype of AO222EHD, skipping annotation <../data/sender.sdf, line 12943>.
ncelab: *W,SDFCTE: Module AO222HHD of instance test_top.s.SDL_5__dc2_s0.U1 does not match SDF celltype of AO222EHD, skipping annotation <../data/sender.sdf, line 13419>.
ncelab: *W,SDFINC: The interconnect src test_top.s.CheckGen_7__wrapperPE.co2.U2.OB is not connected to the destination test_top.s.CheckGen_7__wrapperPE.comp.U3.C1 in instance <../data/sender.sdf, line 573>. The interconnect request will be replaced with a port annotation at the destination.
ncelab: *W,SDFINC: The interconnect src test_top.s.CheckGen_7__wrapperPE.co2.U1.OB is not connected to the destination test_top.s.CheckGen_7__wrapperPE.comp.U1.I in instance <../data/sender.sdf, line 563>. The interconnect request will be replaced with a port annotation at the destination.
ncelab: *W,SDFINC: The interconnect src test_top.s.CheckGen_7__wrapperPE.co2.U2.OB is not connected to the destination test_top.s.CheckGen_7__wrapperPE.U3.I1 in instance <../data/sender.sdf, line 530>. The interconnect request will be replaced with a port annotation at the destination.
ncelab: *W,SDFINC: The interconnect src test_top.s.CheckGen_7__wrapperPE.co2.U2.OB is not connected to the destination test_top.s.CheckGen_7__wrapperPE.U8.I1 in instance <../data/sender.sdf, line 526>. The interconnect request will be replaced with a port annotation at the destination.
ncelab: *W,SDFINC: The interconnect src test_top.s.SDL_15__dc2_s0.U1.O is not connected to the destination test_top.s.CheckGen_7__wrapperPE.co2.U2.S in instance <../data/sender.sdf, line 581>. The interconnect request will be replaced with a port annotation at the destination.
ncelab: *W,SDFINC: The interconnect src test_top.s.SDL_15__dc2_s1.U1.O is not connected to the destination test_top.s.CheckGen_7__wrapperPE.co2.U1.S in instance <../data/sender.sdf, line 584>. The interconnect request will be replaced with a port annotation at the destination.
ncelab: *W,SDFINC: The interconnect src test_top.s.CheckGen_7__wrapperPE.co2.U1.OB is not connected to the destination test_top.s.CheckGen_7__wrapperPE.U2.S in instance <../data/sender.sdf, line 534>. The interconnect request will be replaced with a port annotation at the destination.
ncelab: *W,SDFINC: The interconnect src test_top.s.CheckGen_6__wrapperPE.co2.U3.O is not connected to the destination test_top.s.CheckGen_6__wrapperPE.co2.U1.A in instance <../data/sender.sdf, line 656>. The interconnect request will be replaced with a port annotation at the destination.
ncelab: *W,SDFINC: The interconnect src test_top.s.CheckGen_5__wrapperPE.co2.U2.OB is not connected to the destination test_top.s.CheckGen_5__wrapperPE.comp.U3.C1 in instance <../data/sender.sdf, line 721>. The interconnect request will be replaced with a port annotation at the destination.
ncelab: *W,SDFINC: The interconnect src test_top.s.CheckGen_5__wrapperPE.co2.U1.OB is not connected to the destination test_top.s.CheckGen_5__wrapperPE.comp.U1.I in instance <../data/sender.sdf, line 711>. The interconnect request will be replaced with a port annotation at the destination.
ncelab: *W,SDFINC: The interconnect src test_top.s.CheckGen_5__wrapperPE.co2.U2.OB is not connected to the destination test_top.s.CheckGen_5__wrapperPE.U3.I1 in instance <../data/sender.sdf, line 678>. The interconnect request will be replaced with a port annotation at the destination.
ncelab: *W,SDFINC: The interconnect src test_top.s.CheckGen_5__wrapperPE.co2.U2.OB is not connected to the destination test_top.s.CheckGen_5__wrapperPE.U8.I1 in instance <../data/sender.sdf, line 674>. The interconnect request will be replaced with a port annotation at the destination.
ncelab: *W,SDFINC: The interconnect src test_top.s.SDL_11__dc2_s0.U1.O is not connected to the destination test_top.s.CheckGen_5__wrapperPE.co2.U2.S in instance <../data/sender.sdf, line 729>. The interconnect request will be replaced with a port annotation at the destination.
ncelab: *W,SDFINC: The interconnect src test_top.s.SDL_11__dc2_s1.U1.O is not connected to the destination test_top.s.CheckGen_5__wrapperPE.co2.U1.S in instance <../data/sender.sdf, line 732>. The interconnect request will be replaced with a port annotation at the destination.
ncelab: *W,SDFINC: The interconnect src test_top.s.CheckGen_5__wrapperPE.co2.U1.OB is not connected to the destination test_top.s.CheckGen_5__wrapperPE.U2.S in instance <../data/sender.sdf, line 682>. The interconnect request will be replaced with a port annotation at the destination.
ncelab: *W,SDFINC: The interconnect src test_top.s.CheckGen_4__wrapperPE.co2.U2.OB is not connected to the destination test_top.s.CheckGen_4__wrapperPE.comp.U3.C1 in instance <../data/sender.sdf, line 795>. The interconnect request will be replaced with a port annotation at the destination.
Click to expand...
............................

When I only simulate the sender module with a test_sender including $sdf_annotate("../data/sender.sdf",s). It is right. Only when I combine the two modules, errors appear.
In addition, part of the sender.sdf is (I do not add wire load in the synthesis):
Code: 
(DELAYFILE
(SDFVERSION "OVI 2.1")
(DESIGN "sender")
(DATE "Sat Nov  3 11:44:50 2012")
(VENDOR "fsc0h_d_sc_tc")
(PROGRAM "Synopsys Design Compiler cmos")
(VERSION "C-2009.06-SP5-2")
(DIVIDER /)
(VOLTAGE 1.20:1.20:1.20)
(PROCESS "TCCOM")
(TEMPERATURE 25.00:25.00:25.00)
(TIMESCALE 1ns)
(CELL
  (CELLTYPE "sender")
  (INSTANCE)
  (DELAY
    (ABSOLUTE
    (INTERCONNECT U51/O U86/I1 (0.000:0.000:0.000))
    (INTERCONNECT oa U86/I2 (0.000:0.000:0.000))
    (INTERCONNECT U86/O U85/I (0.000:0.000:0.000))
    (INTERCONNECT U86/O U84/I (0.000:0.000:0.000))
    (INTERCONNECT SDL_14__dc2_s3/U1/O U83/I (0.000:0.000:0.000))
    (INTERCONNECT U83/O U82/I1 (0.000:0.000:0.000))
    (INTERCONNECT U40/O U82/I2 (0.000:0.000:0.000))
    (INTERCONNECT SDL_15__dc2_s3/U1/O U81/I (0.000:0.000:0.000))
    (INTERCONNECT U81/O U80/I1 (0.000:0.000:0.000))
    (INTERCONNECT U38/O U80/I2 (0.000:0.000:0.000))
    (INTERCONNECT SDL_12__dc2_s3/U1/O U79/I (0.000:0.000:0.000))
    (INTERCONNECT U79/O U78/I1 (0.000:0.000:0.000))
    (INTERCONNECT U44/O U78/I2 (0.000:0.000:0.000))
    (INTERCONNECT SDL_13__dc2_s3/U1/O U77/I (0.000:0.000:0.000))
    (INTERCONNECT U77/O U76/I1 (0.000:0.000:0.000))
    (INTERCONNECT U42/O U76/I2 (0.000:0.000:0.000))
    (INTERCONNECT SDL_10__dc2_s3/U1/O U75/I (0.000:0.000:0.000))
    (INTERCONNECT U75/O U74/I1 (0.000:0.000:0.000))
    (INTERCONNECT U48/O U74/I2 (0.000:0.000:0.000))
    (INTERCONNECT SDL_11__dc2_s3/U1/O U73/I (0.000:0.000:0.000))
    (INTERCONNECT U73/O U72/I1 (0.000:0.000:0.000))
    (INTERCONNECT U46/O U72/I2 (0.000:0.000:0.000))
    (INTERCONNECT SDL_8__dc2_s3/U1/O U71/I (0.000:0.000:0.000))
    (INTERCONNECT U71/O U70/I1 (0.000:0.000:0.000))
    (INTERCONNECT U22/O U70/I2 (0.000:0.000:0.000))
    (INTERCONNECT SDL_9__dc2_s3/U1/O U69/I (0.000:0.000:0.000))
    (INTERCONNECT U69/O U68/I1 (0.000:0.000:0.000))
    (INTERCONNECT U20/O U68/I2 (0.000:0.000:0.000))
    (INTERCONNECT SDL_6__dc2_s3/U1/O U67/I (0.000:0.000:0.000))
    (INTERCONNECT U67/O U66/I1 (0.000:0.000:0.000))
    (INTERCONNECT U26/O U66/I2 (0.000:0.000:0.000))
    (INTERCONNECT SDL_7__dc2_s3/U1/O U65/I (0.000:0.000:0.000))
    (INTERCONNECT U65/O U64/I1 (0.000:0.000:0.000))
    (INTERCONNECT U24/O U64/I2 (0.000:0.000:0.000))
    (INTERCONNECT SDL_4__dc2_s3/U1/O U63/I (0.000:0.000:0.000))
    (INTERCONNECT U63/O U62/I1 (0.000:0.000:0.000))
    (INTERCONNECT U30/O U62/I2 (0.000:0.000:0.000))
    (INTERCONNECT SDL_5__dc2_s3/U1/O U61/I (0.000:0.000:0.000))
    (INTERCONNECT U61/O U60/I1 (0.000:0.000:0.000))
    (INTERCONNECT U28/O U60/I2 (0.000:0.000:0.000))
    (INTERCONNECT SDL_2__dc2_s3/U1/O U59/I (0.000:0.000:0.000))
    (INTERCONNECT U59/O U58/I1 (0.000:0.000:0.000))
    (INTERCONNECT U34/O U58/I2 (0.000:0.000:0.000))
    (INTERCONNECT SDL_3__dc2_s3/U1/O U57/I (0.000:0.000:0.000))
    (INTERCONNECT U57/O U56/I1 (0.000:0.000:0.000))
    (INTERCONNECT U32/O U56/I2 (0.000:0.000:0.000))
    (INTERCONNECT SDL_0__dc2_s3/U1/O U55/I (0.000:0.000:0.000))
    (INTERCONNECT U55/O U54/I1 (0.000:0.000:0.000))
    (INTERCONNECT U50/O U54/I2 (0.000:0.000:0.000))
    (INTERCONNECT SDL_1__dc2_s3/U1/O U53/I (0.000:0.000:0.000))
    (INTERCONNECT U53/O U52/I1 (0.000:0.000:0.000))
    (INTERCONNECT U36/O U52/I2 (0.000:0.000:0.000))
    (INTERCONNECT rst U51/I (0.000:0.000:0.000))
    (INTERCONNECT SDL_0__dc2_s0/U1/O U50/I1 (0.000:0.000:0.000))
    (INTERCONNECT SDL_0__dc2_s2/U1/O U50/I2 (0.000:0.000:0.000))
    (INTERCONNECT SDL_0__dc2_s1/U1/O U50/I3 (0.000:0.000:0.000))
    (INTERCONNECT SDL_10__dc2_s0/U1/O U48/I1 (0.000:0.000:0.000))
 ......
//all interconnect are  (0.000:0.000:0.000)
//
  (CELL
  (CELLTYPE "NR2EHD")
  (INSTANCE U86)
  (DELAY
    (ABSOLUTE
    (IOPATH I1 O (0.519:0.519:0.519) (0.222:0.222:0.222))
    (IOPATH I2 O (0.506:0.506:0.506) (0.194:0.194:0.194))
    )
  )
)
(CELL
  (CELLTYPE "BUFEHD")
  (INSTANCE U85)
  (DELAY
    (ABSOLUTE
    (IOPATH I O (0.525:0.525:0.525) (0.366:0.368:0.368))
    )
  )
)
(CELL
  (CELLTYPE "BUFEHD")
  (INSTANCE U84)
  (DELAY
    (ABSOLUTE
    (IOPATH I O (0.507:0.507:0.507) (0.358:0.360:0.360))
    )
  )
)
(CELL
  (CELLTYPE "INVCHD")
  (INSTANCE U83)
  (DELAY
    (ABSOLUTE
    (IOPATH I O (0.049:0.053:0.053) (0.024:0.025:0.025))
    )
  )
)
(CELL
  (CELLTYPE "ND2CHD")
  (INSTANCE U82)
  (DELAY
    (ABSOLUTE
    (IOPATH I1 O (0.066:0.066:0.066) (0.041:0.042:0.042))
    (IOPATH I2 O (0.080:0.086:0.086) (0.039:0.039:0.039))
    )
  )
)
(CELL
  (CELLTYPE "INVCHD")
  (INSTANCE U81)
  (DELAY
    (ABSOLUTE
    (IOPATH I O (0.049:0.053:0.053) (0.024:0.025:0.025))
    )
  )

Hope you can help me. Thank you a lot
 
Last edited by a moderator:

Please can you upload all the sdf and .v files also
 

I am doing something similar and using a VHDL testbench. My gate level netlist is verilog. My testbench is tb.vhd and the component is intantiated in the architecture as "uut : comp port map"

For the scope I am setting "SCOPE = :uut,". But I am still receiving the error "*W,SDFSNF: Specified scope :)uut) not found, skipping annotation of"

Do I need to instantiate the netlist any differently in my testbench or is it the same as if I was instantiating VHDL?
 

You don't need to instantiates the modules in your testbench. As you said, you have a synthesized gate-level netlist which is in verilog. Just try to write a wrapper for the netlist where only the sdf is read and the top module is instantiated. Then in your VHDL testbench, instantiate the new wrapper. I think this will work.
 

In my VHDL testbench, I have only instantiated the netlist with the top level ports.

"uut : comp port map"

But the sdf.cmd file still seems to return an error telling me this can't be found. Is the sdf.cmd file wrong? Should I also include the top level testbench entity in the scope? I've tried numerous combinations, all with the same error.

COMPILED_SDF_FILE = "./comp.sdf.X",
SCOPE = :tb:uut,
LOG_FILE = "sdf.log",
 

I am not quite sure what the problem is. Just show you what to do in Verilog.

The netlist is top.v:

module top(a,b)
input a; output b;
...
endmodule

You create a new wrapper (wrapper.v):

module wrapper(a, b);
input a; output b;
top t(.a(a), .b(b));
..
initial $sdf_annotate("top.sdf", RT, , , "MINIMUM");
endmodule

Then in you testbench file, you use the wrapper module. I think the VHDL is the same to verilog. Just try. In addition, should you use "./comp.sdf.X" or the original sdf generated by DC, I am not sure.




dw_man said:
In my VHDL testbench, I have only instantiated the netlist with the top level ports.

"uut : comp port map"

But the sdf.cmd file still seems to return an error telling me this can't be found. Is the sdf.cmd file wrong? Should I also include the top level testbench entity in the scope? I've tried numerous combinations, all with the same error.

COMPILED_SDF_FILE = "./comp.sdf.X",
SCOPE = :tb:uut,
LOG_FILE = "sdf.log",
Click to expand...
 

The $sdf_annotate command is for verilog only so I have to use a sdf.cmd file to back annotate the compiled SDF. This means I have to use the compiled SDF.

I've tried it with the testbench instantiating the verilog netlist as (uut). I have also tried using the wrapper method a you suggest and then testing the wrapper but I am still receiving the error

ncelab: *W,SDFSNF: Specified scope :)tb:uut:netlist_inst) not found, skipping annotation of ...sdf.X

Has anyone else come across this before or does anyone else have any further suggestions?
 

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