Vhdl testbench required

[sushimushi]

Heya... need help with the testbench code of this division ckt code...plzzz help!!

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all; 

entity div is
generic (
W :integer:= 8; 
CBIT : integer:= 4); -- CBIT=logZ (W)+l)

port (clk , reset : in std_logic ;
start : in std_logic ;
dvsr , dvnd : in std_logic_vector(W-1 downto 0 ) ;
ready , done_tick : out std_logic ;
quo , rmd: out std_logic_vector(W-1 downto 0)) ;
end div ;


architecture Behavioral of div is
type state_type is ( idle , op , last , done ) ;
signal rh_reg ,rh_next : unsigned(W-1 downto 0) ;
signal rl_reg , rl_next : std_logic_vector (W-1 downto 0) ;
signal rh_tmp : unsigned(W-1 downto 0) ;
signal d_reg , d_next : unsigned(W-1 downto 0 ) ;
signal q_bit : std_logic ;
-- f s m d s t a t e a n d d a t a r e g i s t e r s


signal state_reg , state_next : state_type ;
signal n_reg , n_next : unsigned(CBIT - 1 downto 0) ;
begin
process ( clk , reset )
 begin
if reset = '1' then
state_reg <= idle ;
rh_reg <= ( others =>  '0' ) ;
rl_reg <= ( others =>  '0' ) ;
d_reg <= ( others =>  '0' ) ;
n_reg <= ( others =>  '0' ) ;
state_reg <= state_next ;
rh_reg <= rh_next ;
elsif clk'event and clk = '1' then
rl_reg <= rl_next ;
d_reg <= d_next ;
n_reg <= n_next ;
end if ;
end process ;
-- f s m d n e x t - s t a t e l o g i c and d a t a p a t h l o g i c
process ( state_reg , n_reg , rh_reg , rl_reg , d_reg ,start , dvsr , dvnd , q_bit , rh_tmp , n_next )
begin
ready <= '0' ;
done_tick <= '0' ;
state_next <= state_reg ;
rh_next <=  rh_reg  ;
rl_next <=  rl_reg ;
d_next <= d_reg  ;
n_next <= n_reg  ;
case state_reg is
when idle =>
ready <= '1';
if start = '1' then
rh_next <= ( others =>  '0') ;
rl_next <= dvnd ; -- d i v i d e n d
d_next <= unsigned ( dvsr ) ; --d i v i s o r
n_next <= to_unsigned ( W+1 , CBIT); -- i n d e x
state_next <= op ;
end if ;
when op =>
--shift rh and rl left
rl_next <= rl_reg ( W - 2 downto 0 ) & q_bit ;
rh_next<= rh_tmp(W-2 downto 0 ) & rl_reg ( W - 1 ) ;
-- decrease index
n_next <= n_reg - 1;
if  n_next= 1  then
state_next <= last;
end if ;
rl_next <= rl_reg ( W - 2 downto 0 ) & q_bit ;
rh_next <= rh_tmp ;
state_next <= done ;
state_next <= idle ;
done_tick <= '1' ;
state_next <= last ;
when last => 
rl_next <= rl_reg ( W - 2 downto 0 ) & q_bit ;
rh_next <= rh_tmp ;
state_next <= done ;-- l a s t i t e r a t i o n
when done =>
state_next <= idle ;
done_tick <= '1';
end case ;
end process ;
--compare and subtract
process (  rh_reg  , d_reg  )
begin
if  rh_reg  >= d_reg  then
rh_tmp <= rh_reg - d_reg ;
q_bit <= '1' ;
else
rh_tmp <= rh_reg;
q_bit <= '0' ;
end if ;
end process;
quo <= rl_reg;
rmd <= std_logic_vector (rh_reg) ;

end Behavioral;

 

[etoochy]

Hi, recently I discovered that the Xilinx ISE software has a simulator (ISE Simulator) that allows you to simulate your design with a visual test bench, so you dont need to write a code, its so easy. Because I'm a newbie and I found test bench codes horrible. So just try it out I suppose.

Edit: Forgot to mention, it creates a .vhd file, so you can look at the code of the test bench once you made it, if it's coursework or something you might need it if you know what I mean, but definitely you won't learn anything by not writing it.

 

[TrickyDicky]

you appear to have forgotten to add the testbench code that you already write so we can help you with it, because you wouldnt expect us to do your work for you would you?

 

[sushimushi]

heya...actually no that wont help cuz its my project and i have to show the testbench code too...

---------- Post added at 14:09 ---------- Previous post was at 14:06 ----------

you dont have to write the whole code as in.. i just need to know what else would i require to mention thr apart from clk , reset ,start
dvsr , dvnd. cuz its not giving the right answer.

 

[etoochy]

heya...actually no that wont help cuz its my project and i have to show the testbench code too...

---------- Post added at 14:09 ---------- Previous post was at 14:06 ----------

you dont have to write the whole code as in.. i just need to know what else would i require to mention thr apart from clk , reset ,start
dvsr , dvnd. cuz its not giving the right answer.

well you don't write the code but there's a window which you need to configure some settings (like clock high time and all that) and than it gives you another window with your inputs, and you can change your input graphically at different times, and save that. so that saved file is a .vhd file, and you can view it with a notepad or something, you'll see that it's very long test bench code file so you can put in your project but i would suggest you understand it first. just try it, it takes 2 mins if you have the xilinx ise webpack software.

 

[TrickyDicky]

Just noticed something sushimushi - your code is not even going to compile at the moment because you have conflicting libararies.

To fix it - delete std_logic_arith and std_logic_unsigned from your code.