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VHDL testbench enhancement

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paulki

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Hi folks,
I need a help in enhancing my existing testbench with additional functionality. Want to know whether VHDL allows us to use compiler time defines ? ( like Verilog supports as `includes). If any such options are available please share with me. Appreciate all your inputs.

Thanks,
Paul
 

Suudy

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Sort of. VHDL has generics (Verilog calls them parameters). For example:
Code:
entity test is
  generic
  (
    INST_NAME : string := "Entity one";
    BUS_WIDTH : integer := 32
  );
  port
  (
    cs : in std_logic;
    rd : in std_logic;
    wr : in std_logic;
    data : inout std_logic_vector(BUS_WIDTH-1 downto 0)
  );
end entity test;
You can then set the generics when you instantiate a component. For example:
Code:
architecture behav of tb is
  component test is
  generic
  (
    INST_NAME : string := "Entity one";
    BUS_WIDTH : integer := 32
  );
  port
  (
    cs : in std_logic;
    rd : in std_logic;
    wr : in std_logic;
    data : inout std_logic_vector(BUS_WIDTH-1 downto 0)
  );
  end component test;
begin

  test_inst : test
    generic map
    (
      INST_NAME => "Test Instance #1",
      BUS_WIDTH => 16
    );
    port map
    (
      cs => test_cs,
      rd => test_rd,
      wr => test_wr,
      data => test_data
    );
end architecture behav;
Of course, when instantiating a component, the values you pass to the generic map can come from just about anywhere. For example:
Code:
architecture behav of tb is
  const TEST_INST_NAME : string := "Test Instance #1";

  signal test_data : std_logic_vector(47 downto 0);
begin
  test_inst : test
    generic map
    (
      INST_NAME => TEST_INST_NAME
      BUS_WIDTH => test_data'length
    );
    ...
end architecture behav;
And you can pass generics into a generic map. For example:
Code:
entity tb is
  generic
  (
    BUS_WIDTH : integer := 32
  );
  ..
end entity tb;

architecture behav of tb is
begin
  test_inst : test
    generic map
    (
      INST_NAME => "Test Instance",
      BUS_WIDTH => BUS_WIDTH  -- Note that the left hand side is bound to the component and the right hand side is this architecture/entity
    );
    ...
end architecture behav;
The only restriction with generics is that they be statically defined. They cannot be dynamically determined. However, some simulators allow generics to be set at simulation time. If your top level testbench entity has a generic, you may be able to override it at the start of simulation. But once simulation begins, you cannot change that value.

Hope this helps.
 

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