VHDL synthesis problem - number of I/O bound exceeds

[tanzil_dhk]

VHDL synthesis problem

Hi,
I am using xilinx and after i have synthesized my VHDL code for the specific device the report says the number of I/O bound exceeds. I don have much idea about I/O bound. Can anyone explain me what is that?? and how can i decrease that???

Thank You.

 

[flanix]

VHDL synthesis problem

will you delet the unused IO

 

[ruschi]

Re: VHDL synthesis problem

I think the error occurs because your top-level entity has more STD_LOGICs than you have available user-IO on the FPGA - of course this can't be fitted to the device.

As solution you have to wrap it in another entity and serialize the input.
e.g. if you have a design with 128Bit input and output it uses 256 pins of the device. Instead of feeding it with 128 Bit at once transfer 4 cycles a 32Bit word.

I hope it helped
thomas

 

[shanmugaveld]

VHDL synthesis problem

If u r design requires more IO then u have to choose higher order FPGA device.