VHDL Synthesis, ISE errors and mostly warnings

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elockpicker

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hi,

I am a newbie in VHDL programming.I have read a few books about VHDL but when I write a code in ISE ,usually I get errors and mostly warnings (which I don't know what to do).

I think I know the syntax of VHDL but I don't know whats going on in FPGAs .

would you please tell me how to know what's going on in FPGAs so I can write synthesizable and efficient code ?
 

VHDL Synthesis Problems - please help

plz could u clarify what u want to understand exactly?
 

Re: VHDL Synthesis Problems - please help

thank you very much,the problem is solved.

I needed to add 16 blocks of the same type.
I added it as a component an then used port map 16 times.

 

Re: VHDL Synthesis Problems - please help

read ur synthesizer manual to understand errors and warnings easily.
not every vhdl syntax s synthizable
 

Re: VHDL Synthesis Problems - please help

I needed to add 16 blocks of the same type.
I added it as a component an then used port map 16 times.
Click to expand...
That's basically a normal way to design logic. VHDL syntax rules have to be kept however, also basic structural requirements, e.g.
a signal can have only one driver at a time, each input signal of a component must be driven (unless specified with a default value).
 

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